Abstract: Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).

Abstract: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

Abstract: A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.

Abstract: A method for fabricating a metal-oxide-semiconductor device structure. The method includes introducing a dopant species concurrently into a semiconductor active layer that overlies an insulating layer and a gate electrode overlying the semiconductor active layer by ion implantation. The thickness of the semiconductor active layer, the thickness of the gate electrode, and the kinetic energy of the dopant species are chosen such that the projected range of the dopant species in the semiconductor active layer and insulating layer lies within the insulating layer and a projected range of the dopant species in the gate electrode lies within the gate electrode. As a result, the semiconductor active layer and the gate electrode may be doped simultaneously during a single ion implantation and without the necessity of an additional implant mask.

Abstract: A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.

Abstract: An apparatus, system and method for use with a photolithographic system. In accordance with one embodiment, the photolithographic system of the present invention includes a workpiece support member for supporting a semiconductor wafer. A substantially transparent cover member is disposed over the workpiece support member to form a substantially enclosed workpiece cell therebetween. The enclosed workpiece cell is filled with a first immersion fluid having suitable refractive properties. The cover member, having suitable refractive properties, includes an upper surface contoured to form an open reservoir containing a second immersion fluid, having suitable refractive properties, and in which a final lens element may be immersed during a lithography process.

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

Abstract: A photolithographic apparatus, system and method employing an improved refractive medium. The photolithographic apparatus may be used in an immersion lithography system for projecting light onto a workpiece such as a semiconductor wafer. In one embodiment, the photolithographic apparatus includes a container containing a transparent fluid. The fluid container is positioned between a lens element and the wafer. The container is further characterized as having a substantially flexible and transparent bottom membrane contacting an upper surface of the wafer and overlapping at least one side edge of the wafer such that a fluid filled skirt is formed extending beyond the edges of the wafer.

Abstract: A method for forming a gate for a FinFET uses a series of selectively deposited sidewalls along with other sacrificial layers to create a cavity in which a gate can be accurately and reliably formed. This technique avoids long directional etching steps to form critical dimensions of the gate that have contributed to the difficulty of forming FinFETs using conventional techniques. In particular, a sacrificial seed layer, from which sidewalls can be accurately grown, is first deposited over a silicon fin. Once the sacrificial seed layer is etched away, the sidewalls can be surrounded by another disposable layer. Etching away the sidewalls will result in cavities being formed that straddle the fin, and gate conductor material can then be deposited within these cavities. Thus, the height and thickness of the resulting FinFET gate can be accurately controlled by avoiding a long direction etch down the entire height of the fin.

Abstract: Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

Abstract: A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

Abstract: Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

Abstract: A liquid-filled balloon may be positioned between a workpiece, such as a semiconductor structure covered with a photoresist, and a lithography light source. The balloon includes a thin membrane that exhibits good optical and physical properties. Liquid contained in the balloon also exhibits good optical properties, including a refractive index higher than that of air. Light from the lithography light source passes through a mask, through a top layer of the balloon membrane, through the contained liquid, through a bottom layer of the balloon membrane, and onto the workpiece where it alters portions of the photoresist. As the liquid has a low absorption and a higher refractive index than air, the liquid-filled balloon system enhances resolution. Thus, the balloon provides optical benefits of liquid immersion without the complications of maintaining a liquid between (and in contact with) a lithographic light source mechanism and workpiece.

Abstract: An apparatus for immersion optical lithography having a lens capable of relative movement in synchrony with a horizontal motion of a semiconductor wafer in a liquid environment where the synchronous motion of the lens apparatus and semiconductor wafer advantageously reduces the turbulence and air bubbles associated with a liquid environment. The relative motions of the lens and semiconductor wafer are substantially the same as the scanning process occurs resulting in optimal image resolution with minimal air bubbles, turbulence, and disruption of the liquid environment.

Abstract: A field effect transistor employs a vertically oriented carbon nanotube as the transistor body, the nanotube being formed by deposition within a vertical aperture, with an optional combination of several nanotubes in parallel to produced quantized current drive and an optional change in the chemical composition of the carbon material at the top or at the bottom to suppress short channel effects.

Abstract: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract: Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.

Abstract: A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

Abstract: A method for synthesizing carbon nanotubes and structure formed thereby. The method includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded.