Abstract: Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory.

Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Abstract: An indication of a first performance state is received, the first performance state being associated with a first voltage. The first performance state applies to at least one computing system component and the indication is received by a computing system component distinct from the requesting computing system component. An indication of a second performance state is received. The second performance state is associated with a second voltage that is different from the first voltage. It is determined whether the second performance state is within a range defined by a minimum and maximum performance state. Responsive to a determination that the second performance state is within the minimum and maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.

Abstract: Computing system voltage control methods include receiving an indication of a first performance state. The first performance state is associated with a first voltage and applies to at least one computing system component. The indication of the first performance state is received by a first computing system component from a second computing system component. An indication of a second performance state is received, wherein the second performance state is associated with a second voltage that is not equal to the first voltage. It is determined whether the second performance state is within a range defined by a minimum performance state and a maximum performance state. Responsive to determining that the second performance state is within the range defined by the minimum performance state and the maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.

Abstract: A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.

Abstract: Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory.

Abstract: Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory.

Abstract: A distributed power management computer program product is configured to collect power consumption data that indicates power consumption by at least a plurality of the components of a node. The program code can be configured to provide, to each of a plurality of controllers associated with a respective one of the plurality of components, the power consumption data. The program code can be configured to determine a node power consumption. The program code can be configured to determine a power differential as a difference between the node power consumption and an upper power consumption threshold of the node. The program code can be configured to determine a proportion of the node power consumption consumed by a first component. The program code can be configured to compute a local power budget for the first component.

Abstract: Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.

Abstract: A remote debugging technique provides anonymity of program variables and selective debugging capability by providing a registration facility by which program variables are registered locally with a debugging module. An external program then communicates with the debugging modules and observes and/or modifies the program variables by specifying either an index or a variable name. The need to publish symbols is thereby averted and only the variables that a developer is interested in observing need be registered.

Abstract: Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.

Abstract: A remote debugging technique provides anonymity of program variables and selective debugging capability by providing a registration facility by which program variables are registered locally with a debugging module. An external program then communicates with the debugging modules and observes and/or modifies the program variables by specifying either an index or a variable name. The need to publish symbols is thereby averted and only the variables that a developer is interested in observing need be registered.

Abstract: An apparatus includes memory, a processor coupled to the memory, and a set of one or more frequency target monitors. The processor includes a set of one or more processor cores, and the set of one or more frequency target monitors are coupled to the set of one or more processor cores. Each frequency target monitor is configured to determine a difference between an actual performance and an expected performance of a processor core from the set of one or more processor cores. Each frequency target monitor is also configured to, responsive to determining the difference between the actual performance and the expected performance of the processor core from the set of one or more processor cores, record an indication of a difference between the actual performance and the expected performance of the processor core from the set of one or more processor cores.

Abstract: A system, method and computer program product for enabling efficient and accurate post-silicon leakage power characterization of semiconductor chips at very high temperatures. The system and method can be used to estimate dynamic power usage at a sub-component level. The system and method determines leakage power during test time while running a workload in a manner such that a wider range of temperatures can be characterized on a tester that does not have precise temperature control, i.e., does not require or use external heaters. Additional power management functionality for a semiconductor device is provided while running a workload that breaks down total power measured into workload dependent and workload-independent subcomponents.

Abstract: A mechanism is provided for dynamic power and thermal capping in a flash storage system. A set of measurement values are received for the flash storage system, the set of measurement values comprising one or more of a set of current (I) measurement values, a set of voltage (V) measurement values, or a set of temperature (T) measurement values. An average current (Iavg) value from the set of current (I) measurements and, responsive to the average current (Iavg) value being greater than a predetermined maximum current (Imax) value, a determination is made as to whether a rate at which erase operations are performed for the flash storage system is greater than a predetermined minimum erase rate. Responsive to the rate at which erase operations are performed for the flash storage system being greater than the predetermined minimum erase rate, the rate at which erase operations are performed for the flash storage system are decreased by a predetermined value.

Abstract: A mechanism is provided for minimizing system power in the data processing system with fast convergence. A current aggregate system power value is determined using a current thermal threshold value. For each potential thermal threshold value in a set of potential thermal threshold values, a determination is made as to whether there is a potential thermal threshold value that results in a potential aggregate system power value that is lower than the current aggregate system power value. Responsive to identifying an optimal potential thermal threshold value from the set of potential thermal threshold values that results in minimum aggregate system power value that is lower than the current aggregate system power value, the optimal potential thermal threshold value is set as a new thermal threshold value.

Abstract: A mechanism is provided for minimizing system power in the data processing system with fast convergence. A current aggregate system power value is determined using a current thermal threshold value. For each potential thermal threshold value in a set of potential thermal threshold values, a determination is made as to whether there is a potential thermal threshold value that results in a potential aggregate system power value that is lower than the current aggregate system power value. Responsive to identifying an optimal potential thermal threshold value from the set of potential thermal threshold values that results in minimum aggregate system power value that is lower than the current aggregate system power value, the optimal potential thermal threshold value is set as a new thermal threshold value.

Abstract: A system, method and computer program product for enabling efficient and accurate post-silicon leakage power characterization of semiconductor chips at very high temperatures. The system and method can be used to estimate dynamic power usage at a sub-component level. The system and method determines leakage power during test time while running a workload in a manner such that a wider range of temperatures can be characterized on a tester that does not have precise temperature control, i.e., does not require or use external heaters. Additional power management functionality for a semiconductor device is provided while running a workload that breaks down total power measured into workload dependent and workload-independent subcomponents.

Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.

Abstract: A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified.