Abstract: The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

Abstract: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: An electrostatic discharge protection circuit. The electrostatic discharge (ESD) circuit utilizes inductors and resistors added to sources of multiple fingers of the NMOS transistor, which is triggered by some feedback circuit uniformly. When under an ESD zapping, a finger MOS transistor is trigger initially to snapback region owing to its layout or other causes, a voltage drop across the inductor or the resistor connected to the source of the finger MOS transistor is occurred and presented to gates of the other finger MOS transistors by the feedback circuit. Thus, the other finger MOS transistors are turned on.

Abstract: A circuit for protecting a power amplifier from electrostatic discharge (ESD) that comprises a clamp circuit connected between a first power line and a connection line, and a detecting circuit connected between the connection line and a second power line for detecting whether an ESD event occurs at a conductive pad coupled to the power amplifier and activating the clamp circuit in response to an ESD event, wherein an ESD current due to the ESD event is conducted by the clamp circuit to the first power line.

Abstract: A buffer circuit on a first chip coupled between a first circuit on the first chip and a second circuit on a second chip including a driver circuit comprising at least a first PMOS transistor and a second PMOS transistor, one of the source and drain of the second PMOS transistor being coupled to the substrate of the first PMOS transistor, wherein the second PMOS transistor is turned off when a first signal having a voltage level higher than a power supply voltage of the buffer circuit appears at the node, and a gate-tracking circuit coupled to provide a first bias and a second bias to the gate of the first PMOS transistor depending on the signal appearing at the node.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.

Abstract: A buffer circuit on a first chip coupled between a first circuit on the first chip and a second circuit on a second chip including a driver circuit comprising at least a first PMOS transistor and a second PMOS transistor, one of the source and drain of the second PMOS transistor being coupled to the substrate of the first PMOS transistor, wherein the second PMOS transistor is turned off when a first signal having a voltage level higher than a power supply voltage of the buffer circuit appears at the node, and a gate-tracking circuit coupled to provide a first bias and a second bias to the gate of the first PMOS transistor depending on the signal appearing at the node.

Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

Abstract: A mixed-voltage I/O buffer circuit that prevents leakages through a driver stage PMOS transistor is provided. The buffer circuit has a first part that prevents leakage through a parasitic diode of the transistor and a second part that prevents leakage through the transistor when the transistor is turned on by a signal on a bonding pad having a voltage level higher than a power supply voltage of the buffer circuit. The buffer circuit provides biases approximately equal to the high voltage signal to a gate and a substrate terminal of the PMOS transistor when the bonding pad has the high voltage signal thereon, and provides a bias approximately equal to the power supply voltage of the buffer circuit to the gate and substrate of the PMOS transistor when the bonding pad has a low voltage signal thereon.