Abstract: A mixed-voltage I/O buffer circuit that prevents leakages through a driver stage PMOS transistor is provided. The buffer circuit has a first part that prevents leakage through a parasitic diode of the transistor and a second part that prevents leakage through the transistor when the transistor is turned on by a signal on a bonding pad having a voltage level higher than a power supply voltage of the buffer circuit. The buffer circuit provides biases approximately equal to the high voltage signal to a gate and a substrate terminal of the PMOS transistor when the bonding pad has the high voltage signal thereon, and provides a bias approximately equal to the power supply voltage of the buffer circuit to the gate and substrate of the PMOS transistor when the bonding pad has a low voltage signal thereon.

Abstract: An electrostatic discharge protection circuit. The electrostatic discharge (ESD) circuit utilizes inductors and resistors added to sources of multiple fingers of the NMOS transistor, which is triggered by some feedback circuit uniformly. When under an ESD zapping, a finger MOS transistor is trigger initially to snapback region owing to its layout or other causes, a voltage drop across the inductor or the resistor connected to the source of the finger MOS transistor is occurred and presented to gates of the other finger MOS transistors by the feedback circuit. Thus, the other finger MOS transistors are turned on.

Abstract: A substrate-triggered ESD protection component having dummy gate structures. The ESD protection component includes a bipolar junction transistor (BJT), a substrate-triggering region to provide triggering current and a dummy gate structure. The BJT comprises a collector. The dummy gate structure has a poly-silicon gate adjacent to the collector and the substrate-triggering region. The emitter of the BJT is coupled to a power line, the collector is coupled to a pad, and the substrate-triggering region is coupled to an ESD detection circuit. During normal circuit operations, a base of the BJT is coupled with the power line through the ESD detection circuit to keep the BJT off. When an ESD event occurs between the pad and the power line, a triggering current is provided to the substrate-triggering region by the ESD detection circuit to trigger on the BJT and release ESD current.

Abstract: A substrate-triggered ESD protection component having dummy gate structures. The ESD protection component includes a bipolar junction transistor (BJT), a substrate-triggering region to provide triggering current and a dummy gate structure. The BJT comprises a collector. The dummy gate structure has a poly-silicon gate adjacent to the collector and the substrate-triggering region. The emitter of the BJT is coupled to a power line, the collector is coupled to a pad, and the substrate-triggering region is coupled to an ESD detection circuit. During normal circuit operations, a base of the BJT is coupled with the power line through the ESD detection circuit to keep the BJT off. When an ESD event occurs between the pad and the power line, a triggering current is provided to the substrate-triggering region by the ESD detection circuit to trigger on the BJT and release ESD current.

Abstract: Hybrid diodes with excellent ESD protection capacity. Each hybrid diode has two diodes: one is a poly-bounded diode formed as a junction between a substrate and a diffusion region thereon, the other is a poly diode formed as a poly gate having two regions with different conductivity. The poly-bounded diode and the poly diode are connected in series or in parallel to form a hybrid diode. The parallel hybrid diode has smaller operation resistance and as a result better ESD robustness. The series hybrid diode has lower capacitance load and is especially suitable for the ESD protection in high-speed or radio frequency integrated circuit input/output design. The hybrid diode can also be applied in the ESD protection circuit in an input/output port, a power-rail ESD clamp circuit, and a whole-chip ESD protection system. The hybrid diodes can be also implemented in the silicon-on-insulator (SOI) CMOS process.

Abstract: Hybrid diodes with excellent ESD protection capacity. Each hybrid diode has two diodes: one is a poly-bounded diode formed as a junction between a substrate and a diffusion region thereon, the other is a poly diode formed as a poly gate having two regions with different conductivity. The poly-bounded diode and the poly diode are connected in series or in parallel to form a hybrid diode. The parallel hybrid diode has smaller operation resistance and as a result better ESD robustness. The series hybrid diode has lower capacitance load and is especially suitable for the ESD protection in high-speed or radio frequency integrated circuit input/output design. The hybrid diode can also be applied in the ESD protection circuit in an input/output port, a power-rail ESD clamp circuit, and a whole-chip ESD protection system. The hybrid diodes can be also implemented in the silicon-on-insulator (SOI) CMOS process.