Patents by Inventor Che-Ming Hsu
Che-Ming Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20240099154Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: UNITED MICROELECTRONICS CORPInventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
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Publication number: 20240087961Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Ju CHOU, Chih-Chung Chang, Jun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Kao, Chen-Hsuan Liao
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Patent number: 11923250Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.Type: GrantFiled: July 28, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
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Publication number: 20240069277Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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Publication number: 20230387125Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.Type: ApplicationFiled: July 31, 2023Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien HUANG, Che-Ming HSU, Ching-Feng FU, Huan-Just LIN
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Patent number: 11769770Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.Type: GrantFiled: May 6, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien Huang, Che-Ming Hsu, Ching-Feng Fu, Huan-Just Lin
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Patent number: 11761450Abstract: A rotation locking system of a motor of a fan is provided. A closed-loop control circuit outputs an initial duty cycle signal according to a current rotational speed and a target rotational speed. A driver circuit outputs a driving signal to the motor to drive the motor to rotate according to the initial duty cycle signal. A lookup table arithmetic circuit looks up, from a lookup table, two reference duty cycles correspond to two reference rotational speeds that are respectively equal to the current rotational speed and the target rotational speed. The lookup table arithmetic circuit calculates a difference between the two reference duty cycles. A speed feedback control circuit compensates the initial duty cycle signal according to the difference to output a final duty cycle signal to the driver circuit. The driver circuit drives the motor to rotate according to the final duty cycle signal.Type: GrantFiled: November 30, 2021Date of Patent: September 19, 2023Assignee: ANPEC ELECTRONICS CORPORATIONInventors: Che-Ming Hsu, Kun-Min Chen
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Publication number: 20230230884Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Che-Ming Hsu
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Publication number: 20230121435Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Lien Huang, Ching-Feng Fu, Guan-Ren Wang, Che-Ming Hsu
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Patent number: 11626326Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.Type: GrantFiled: February 3, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Che-Ming Hsu
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Patent number: 11621221Abstract: A package substrate is adapted to a ball grid array package. The substrate includes two substrate contacts, two solder ball pads, two via holes and two signal lines. A connection line of the two substrate contacts is substantially perpendicular to a connection line of the two solder ball pads. The two substrate contacts are respectively connected to the two via holes by the two signal lines. Each signal line includes a circuit trace section, an approaching section and a bifurcating section connected in sequence. The two circuit trace sections of each signal line are substantially arranged in parallel. The two approaching sections are substantially arranged in parallel and substantially symmetrical about the connection line of the solder ball pads. The two bifurcating sections are substantially symmetrical about the pad connection line and respectively electrically connected to the two via holes.Type: GrantFiled: May 11, 2021Date of Patent: April 4, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Che-Ming Hsu, Sung-Yuan Lin, Nai-Jen Hsuan, Yu-Hsin Wang
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Publication number: 20230049456Abstract: A rotation locking system of a motor of a fan is provided. A closed-loop control circuit outputs an initial duty cycle signal according to a current rotational speed and a target rotational speed. A driver circuit outputs a driving signal to the motor to drive the motor to rotate according to the initial duty cycle signal. A lookup table arithmetic circuit looks up, from a lookup table, two reference duty cycles correspond to two reference rotational speeds that are respectively equal to the current rotational speed and the target rotational speed. The lookup table arithmetic circuit calculates a difference between the two reference duty cycles. A speed feedback control circuit compensates the initial duty cycle signal according to the difference to output a final duty cycle signal to the driver circuit. The driver circuit drives the motor to rotate according to the final duty cycle signal.Type: ApplicationFiled: November 30, 2021Publication date: February 16, 2023Inventors: CHE-MING HSU, KUN-MIN CHEN
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Publication number: 20230008165Abstract: A method is provided for sealing a seam in a self-aligned contact (SAC) layer that is disposed on a gate of a semiconductor structure. The method includes depositing a filler in the seam to seal the seam.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Che-Ming HSU
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Patent number: 11532712Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.Type: GrantFiled: February 3, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yu-Lien Huang, Ching-Feng Fu, Guan-Ren Wang, Che-Ming Hsu
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Publication number: 20220359516Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.Type: ApplicationFiled: May 6, 2021Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien HUANG, Che-Ming HSU, Ching-Feng FU, Huan-Just LIN
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Patent number: 11367378Abstract: A driving method includes the following steps: driving a first dummy pixel circuit according to a first test signal, and driving a display pixel circuit according to a driving signal, wherein the first test signal is maintained at a value corresponding to a first gray level; detecting a detection voltage change value cross a light-emitting element in the display pixel circuit is driven for a driving time, and detecting a first test voltage change value cross a light-emitting element in the first dummy pixel circuit is driven for the driving time; and adjusting the driving signal according to the detection voltage change value, the first test voltage change value and a second test voltage change value, wherein the second test voltage change value is obtained by detecting a second dummy pixel circuit or from a memory unit.Type: GrantFiled: April 20, 2021Date of Patent: June 21, 2022Assignee: AU OPTRONICS CORPORATIONInventors: Pei-Lin Hsieh, Che-Ming Hsu
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Publication number: 20220139817Abstract: A package substrate is adapted to a ball grid array package. The substrate includes two substrate contacts, two solder ball pads, two via holes and two signal lines. A connection line of the two substrate contacts is substantially perpendicular to a connection line of the two solder ball pads. The two substrate contacts are respectively connected to the two via holes by the two signal lines. Each signal line includes a circuit trace section, an approaching section and a bifurcating section connected in sequence. The two circuit trace sections of each signal line are substantially arranged in parallel. The two approaching sections are substantially arranged in parallel and substantially symmetrical about the connection line of the solder ball pads. The two bifurcating sections are substantially symmetrical about the pad connection line and respectively electrically connected to the two via holes.Type: ApplicationFiled: May 11, 2021Publication date: May 5, 2022Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Che-Ming Hsu, Sung-Yuan Lin, Nai-Jen Hsuan, Yu-Hsin Wang
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Publication number: 20220005396Abstract: A driving method includes the following steps: driving a first dummy pixel circuit according to a first test signal, and driving a display pixel circuit according to a driving signal, wherein the first test signal is maintained at a value corresponding to a first gray level; detecting a detection voltage change value cross a light-emitting element in the display pixel circuit is driven for a driving time, and detecting a first test voltage change value cross a light-emitting element in the first dummy pixel circuit is driven for the driving time; and adjusting the driving signal according to the detection voltage change value, the first test voltage change value and a second test voltage change value, wherein the second test voltage change value is obtained by detecting a second dummy pixel circuit or from a memory unit.Type: ApplicationFiled: April 20, 2021Publication date: January 6, 2022Inventors: Pei-Lin HSIEH, Che-Ming HSU