Patents by Inventor Chee Seng Foong
Chee Seng Foong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150262924Abstract: A semiconductor package includes a lead frame having an interior region and leads surrounding the interior region, an integrated circuit, a region of insulating material, and a power bar. The integrated circuit, which is disposed in the interior region, has bond pads and electrical couplings (e.g., bond wires) between the bond pads and the leads. The region of insulating material is disposed on at least some of the lead frame leads and the power bar is disposed on the region of insulating material. There also are electrical couplings between the power bar and at least some of the bond pads.Type: ApplicationFiled: March 11, 2014Publication date: September 17, 2015Inventors: Kong Bee Tiu, Chee Seng Foong, Wai Yew Lo
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Patent number: 9134193Abstract: A stacked die sensor package includes a die paddle and lead fingers that surround the die paddle. The lead fingers have proximal ends near the die paddle and distal ends spaced from the die paddle. A first semiconductor die is mounted to one side of the die paddle and electrically connected to the lead fingers with first bond wires. A sensor die is mounted to the other side of the die paddle and electrically connected to the lead fingers with sensor bond wires. An encapsulation material covers the first die and the first bond wires, while a gel material and a lid cover the sensor die and the sensor bond wires. The package may also have a second semiconductor die attached on an active surface of the first die and electrically connected one or both of the lead fingers or first die bonding pads with second bond wires.Type: GrantFiled: December 6, 2013Date of Patent: September 15, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Lau Teck Beng, Sheng Ping Took
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Publication number: 20150235924Abstract: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Inventors: Chee Seng Foong, Meng Kong Lye, Lan Chu Tan, Seng Kiong Teng
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Publication number: 20150201489Abstract: A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Inventors: Chee Seng Foong, Lan Chu Tan
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Publication number: 20150200177Abstract: A semiconductor device is assembled where a signal redistribution layer is formed over a partially encapsulated semiconductor die. The distribution layer is formed by selectively coating a first electrical insulating layer over an active surface of the die and a surrounding portion of the encapsulation material, where die bonding pads on the active surface of the die are exposed through access apertures in the first electrical insulating layer. A layer of metallic powder is deposited onto the first insulating layer and then electrically conductive runners are formed from the layer of metallic powder. The runners are coated with a further electrical insulating layer. A mounting area of each runner is exposed through an external connection aperture. Solder balls may be attached to the mounting areas.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Inventors: CHEE SENG FOONG, Lan Chu Tan
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Publication number: 20150183131Abstract: A dicing blade suitable for cutting a semiconductor wafer has an edge of fine grit for polishing a top surface of the wafer and a protruding part of coarse grit for making an initial cut into the wafer. The blade reduces chipping of the top surface of the wafer and increases throughput by facilitating cutting and polishing in one operation. The blade can dice and polish comparatively thick wafers having narrow scribe lines in a single operation.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Inventors: Chee Seng Foong, Wen Shi Koh, Kai Yun Yow
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Publication number: 20150160087Abstract: A stacked die sensor package includes a die paddle and lead fingers that surround the die paddle. The lead fingers have proximal ends near the die paddle and distal ends spaced from the die paddle. A first semiconductor die is mounted to one side of the die paddle and electrically connected to the lead fingers with first bond wires. A sensor die is mounted to the other side of the die paddle and electrically connected to the lead fingers with sensor bond wires. An encapsulation material covers the first die and the first bond wires, while a gel material and a lid cover the sensor die and the sensor bond wires. The package may also have a second semiconductor die attached on an active surface of the first die and electrically connected one or both of the lead fingers or first die bonding pads with second bond wires.Type: ApplicationFiled: December 6, 2013Publication date: June 11, 2015Inventors: Chee Seng Foong, Lau Teck Beng, Sheng Ping Took
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Patent number: 9053972Abstract: A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.Type: GrantFiled: November 21, 2013Date of Patent: June 9, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Lan Chu Tan
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Patent number: 9040335Abstract: A semiconductor sensor device has a pressure sensing die and at least one other die mounted on a substrate, and electrical interconnections that interconnect the pressure sensing die and the at least one other die. An active region of the pressure sensing die is covered with a pressure sensitive gel material, and a cap having a cavity is mounted over the pressure sensing die such that the pressure sensing die is positioned within the cavity. The cap has a side vent hole that exposes the gel covered active region of the pressure sensing die to ambient atmospheric pressure outside the sensor device. Molding compound on an upper surface of the substrate encapsulates the at least one other die and at least a portion of the cap.Type: GrantFiled: September 17, 2013Date of Patent: May 26, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Low Boon Yew, Chee Seng Foong, Teck Beng Lau
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Publication number: 20150137354Abstract: A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Inventors: Chee Seng Foong, Lan Chu Tan
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Publication number: 20150076630Abstract: A semiconductor sensor device has a pressure sensing die and at least one other die mounted on a substrate, and electrical interconnections that interconnect the pressure sensing die and the at least one other die. An active region of the pressure sensing die is covered with a pressure sensitive gel material, and a cap having a cavity is mounted over the pressure sensing die such that the pressure sensing die is positioned within the cavity. The cap has a side vent hole that exposes the gel covered active region of the pressure sensing die to ambient atmospheric pressure outside the sensor device. Molding compound on an upper surface of the substrate encapsulates the at least one other die and at least a portion of the cap.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Inventors: Boon Yew Low, Chee Seng Foong, Lau Teck Beng
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Publication number: 20150069603Abstract: Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.Type: ApplicationFiled: September 8, 2013Publication date: March 12, 2015Inventors: Chee Seng Foong, Boon Yew Low, Navas Khan Oratti Kalandar
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Publication number: 20150054099Abstract: A semiconductor sensor device is assembled using a pre-molded lead frame having first and second die flags. The first die flag includes a cavity. A pressure sensor die (P-cell) is mounted within the cavity and a master control unit die (MCU) is mounted to the second flag. The P-cell and MCU are electrically connected to leads of the lead frame with bond wires. The die attach and wire bonding steps are each done in a single pass. A mold pin is placed over the P-cell and then the MCU is encapsulated with a mold compound. The mold pin is removed leaving a recess that is next filled with a gel material. Finally a lid is placed over the P-cell and gel material. The lid includes a hole that that exposes the gel-covered active region of the pressure sensor die to ambient atmospheric pressure outside the sensor device.Type: ApplicationFiled: August 25, 2013Publication date: February 26, 2015Inventors: Kai Yun Yow, Poh Leng Eu, Chee Seng Foong, Navas Khan Oratti Kalandar, Lan Chu Tan
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Publication number: 20140306336Abstract: A fluid cooled semiconductor die package includes a package support substrate with a die mounting surface and an opposite package mounting surface. The package support substrate has external connector solder deposits on respective external connector pads of the package mounting surface, and a package fluid inlet duct and a package fluid outlet duct each providing fluid communication between the die mounting surface and package mounting surface. A semiconductor die is mounted on the die mounting surface. The die has external terminals electrically connected to the external connector pads. An inlet solder deposit is soldered to an inlet pad of the package mounting surface. The inlet pad surrounds an entrance of the fluid inlet duct. An outlet solder deposit is soldered to an outlet pad of the package mounting surface. The outlet pad surrounds an exit of the package fluid inlet duct.Type: ApplicationFiled: April 15, 2013Publication date: October 16, 2014Inventors: Chee Seng Foong, Tim V. Pham
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Patent number: 8860212Abstract: A fluid cooled semiconductor die package includes a package support substrate with a die mounting surface and an opposite package mounting surface. The package support substrate has external connector solder deposits on respective external connector pads of the package mounting surface, and a package fluid inlet duct and a package fluid outlet duct each providing fluid communication between the die mounting surface and package mounting surface. A semiconductor die is mounted on the die mounting surface. The die has external terminals electrically connected to the external connector pads. An inlet solder deposit is soldered to an inlet pad of the package mounting surface. The inlet pad surrounds an entrance of the fluid inlet duct. An outlet solder deposit is soldered to an outlet pad of the package mounting surface. The outlet pad surrounds an exit of the package fluid inlet duct.Type: GrantFiled: April 15, 2013Date of Patent: October 14, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Tim V. Pham
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Publication number: 20140231977Abstract: A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface of the first die. A surface of a second semiconductor die is bonded to the stud bumps. The first main surface of the first die is wire bonded to the first main surface of the support. The first and second dies, the stud bumps, the bond wire, and at least a portion of the first main surface of the support are encapsulated with a mold compound.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Inventors: Navas Khan Oratti Kalandar, Chee Seng Foong, Kesvakumar V.C. Muniandy
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Patent number: 8810020Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.Type: GrantFiled: June 22, 2012Date of Patent: August 19, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Navas Khan Oratti Kalandar, Chee Seng Foong, Norazham Mohd Sukemi, Kesvakumar V. C. Muniandy
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Patent number: 8643172Abstract: A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader is generally T-shaped in cross-section. The top portion has a hole at its center that extends from a top surface of the top portion to the at least one channel of the base portion. Mold compound is injected through the hole and out through the channels.Type: GrantFiled: June 8, 2007Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Aminuddin Ismail, Heng Keong Yip
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Publication number: 20130341796Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Navas Khan Oratti Kalandar, Chee Seng Foong, Norazham Mohd Sukemi, Kesvakumar V.C. Muniandy
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Patent number: 8415779Abstract: A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die. The lead frame includes a die support area for receiving and supporting the IC die and a plurality of leads surrounding the die support area. A plurality of interconnect receiving portions is formed in the die support area. The interconnect receiving portions are for providing electrical interconnection to first bumps on a bottom surface of the IC die. The leads are for providing electrical interconnection to second bumps on a surface of the IC die, the second bumps surrounding the first bumps.Type: GrantFiled: March 15, 2011Date of Patent: April 9, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Tzu Ling Wong, Chee Seng Foong, Kai Yun Yow