Patents by Inventor Chee Seng Foong
Chee Seng Foong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8049313Abstract: A heat spreader (50) for a semiconductor package (100) includes a heat dissipating portion (52) having a recessed periphery (54). A thermosetting resin (58) is disposed in the recessed periphery (54). The heat spreader (50) may include a heat absorbing portion (56) coupled to the heat dissipating portion (52).Type: GrantFiled: September 20, 2006Date of Patent: November 1, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Kim Chiew Ho
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Publication number: 20110248390Abstract: A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die. The lead frame includes a die support area for receiving and supporting the IC die and a plurality of leads surrounding the die support area. A plurality of interconnect receiving portions is formed in the die support area. The interconnect receiving portions are for providing electrical interconnection to first bumps on a bottom surface of the IC die. The leads are for providing electrical interconnection to second bumps on a surface of the IC die, the second bumps surrounding the first bumps.Type: ApplicationFiled: March 15, 2011Publication date: October 13, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Tzu Ling WONG, Chee Seng FOONG, Kai Yun YOW
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Patent number: 7566648Abstract: A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A second etching operation is performed on the metal layer to form the solder pad. A solder mask is formed on the substrate and a portion of the solder pad.Type: GrantFiled: April 22, 2007Date of Patent: July 28, 2009Assignee: Freescale Semiconductor Inc.Inventors: Heng Keong Yip, Thoon Khin Chang, Chee Seng Foong
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Patent number: 7554185Abstract: A semiconductor package and method of forming the package, including a substrate having an opening formed therein. Contact pads are formed about a periphery of the opening on a first side of the substrate and a second opposing side of the substrate. A flip chip die is mounted to the substrate, having an active side mounted on a first side of the substrate and in electrical communication with at least some of the contact pads formed on the first side of the substrate. At least one wire bond die is mounted through the opening, with a non-active side mounted on the active side of the flip chip die. The wire bond die is in electrical communication with at least some of the plurality of contact pads formed on the second opposing side of the substrate.Type: GrantFiled: October 31, 2005Date of Patent: June 30, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Aminuddin Ismail, Wai Yew Lo, Bee Hoon Liau, Jin- Mei Liu, Jian- Hong Wang, Jin- Zhong Yao, Fu- Bin Song
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Publication number: 20080305584Abstract: A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader is generally T-shaped in cross-section. The top portion has a hole at its center that extends from a top surface of the top portion to the at least one channel of the base portion. Mold compound is injected through the hole and out through the channels.Type: ApplicationFiled: June 8, 2007Publication date: December 11, 2008Inventors: Chee Seng Foong, Aminuddin Ismail, Heng Keong Yip
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Patent number: 7452750Abstract: A method of attaching a capacitor (112) to a substrate (100) includes applying a flux (108) to respective capacitor pads (104, 106) on the substrate (100). The capacitor (112) is placed on the fluxed capacitor pads (104, 106) and a reflow operation is performed on the capacitor (112) and the substrate (100) such that intermetallic interconnects (128) are formed between the capacitor (112) and the substrate (100).Type: GrantFiled: February 28, 2006Date of Patent: November 18, 2008Assignee: Freescale Semiconductor, IncInventors: Wai Yew Lo, Chee Seng Foong
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Publication number: 20080258297Abstract: A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A second etching operation is performed on the metal layer to form the solder pad. A solder mask is formed on the substrate and a portion of the solder pad.Type: ApplicationFiled: April 22, 2007Publication date: October 23, 2008Inventors: Heng Keong YIP, Thoon Khin Chang, Chee Seng Foong
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Patent number: 7432130Abstract: A method of packaging a semiconductor die (10) includes providing a flip-chip die (10) with bump connections (12) on its bottom surface (14). An adhesive tape (18) is attached to a plate surface (16) and lead fingers (20) are formed on the tape (18). The die (10) is placed on the tape (18) such that the bumps (12) on the die (10) contact respective ones of the lead fingers (20) on the tape (18). A reflow process is performed on the die (10), the tape (18) and the plate (16), which forms C5 type interconnects. A mold compound (24) is formed over the die (10) and the tape (18), and then the tape (18) and the plate (16) are removed.Type: GrantFiled: January 27, 2006Date of Patent: October 7, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Aminuddin Ismail, Chee Seng Foong, Ruzaini Ibrahim
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Publication number: 20080111248Abstract: A semiconductor package (100, 150, 200, 250), and method of forming the package, including a substrate (102, 102?, 202, 202?) having an opening (104, 104?, 204, 204?) formed therein. Contact pads (112, 112?, 212, 212?) are formed about a periphery of the opening on a first side of the substrate (106, 106?, 206, 206?) and a second opposing side (132, 132?, 232, 232?) of the substrate. A flip chip die (120, 120?, 220, 220?) is mounted to the substrate, having an active side (114, 114?, 214, 214?) mounted on a first side of the substrate and in electrical communication with at least some of the contact pads formed on the first side of the substrate. At least one wire bond die (110, 110?, 210, 210?) is mounted through the opening, with a non-active side mounted on the active side of the flip chip die. The wire bond die is in electrical communication with at least some of the plurality of contact pads formed on the second opposing side of the substrate.Type: ApplicationFiled: October 31, 2005Publication date: May 15, 2008Inventors: Chee Seng Foong, Aminuddin Ismail, Wai Yew Lo, Bee Hoon Liau, Jin-Mei Liu, Jian-Hong Wang, Jin-Zhong Yao, Fu-Bin Song
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Publication number: 20080067645Abstract: A heat spreader (50) for a semiconductor package (100) includes a heat dissipating portion (52) having a recessed periphery (54). A thermosetting resin (58) is disposed in the recessed periphery (54). The heat spreader (50) may include a heat absorbing portion (56) coupled to the heat dissipating portion (52).Type: ApplicationFiled: September 20, 2006Publication date: March 20, 2008Inventors: Chee Seng Foong, Kim Chiew Ho
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Patent number: 7285855Abstract: A method of packaging an integrated circuit die (12) includes the steps of loading an array of soft conductive balls into recesses formed in a platen and locating the platen in a first part of a mold cavity. A second part of the mold is pressed against the balls to flatten a surface of the balls. A first mold compound then is injected into the mold cavity such that the mold compound surrounds exposed portions of the balls. The balls are removed from the platen and a first side of an integrated circuit die is attached to the balls such that the die is surrounded by the balls. Die bonding pads on a second side of the die are electrically connected to respective ones of the balls surrounding the die, and then the die, the electrical connections, and a top portion of the conductive balls is encapsulated with a second mold compound. The result is an encapsulated IC having a bottom side with exposed balls.Type: GrantFiled: January 22, 2007Date of Patent: October 23, 2007Assignee: Freescale Semiconductor, IncInventor: Chee Seng Foong
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Patent number: 7179682Abstract: A method of packaging an integrated circuit die includes the steps of loading an array of soft conductive balls into recesses formed in a platen and locating the platen in a first part of a mold cavity. A second part of the mold is pressed against the balls to flatten a surface of the balls. A first mold compound then is injected into the mold cavity such that the mold compound surrounds exposed portions of the balls. The balls are removed from the platen and a first side of an integrated circuit die is attached to the balls. Die bonding pads on a second side of the die are electrically connected to respective ones of the balls surrounding the die, and then the die, the electrical connections, and a top portion of the conductive balls is encapsulated with a second mold compound.Type: GrantFiled: July 27, 2005Date of Patent: February 20, 2007Assignee: Freescale Semiconductor, Inc.Inventor: Chee Seng Foong
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Patent number: 6900531Abstract: An image sensor device is made using an ultra-thin substrate so that the overall device height is less than 1.0 mm. The image sensor includes a flexible circuit substrate having first and second opposing sides, the first side having a central area and an outer, bonding pad area including bonding pads. A sensor integrated circuit (IC) is attached to the central area of the first side of the circuit substrate. The IC has an active area and a peripheral bonding pad area including bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the circuit substrate bonding pads to electrically connect the IC and the circuit substrate. A wall having a first end with a step and a second end has its second end attached to an outer portion beyond the outer bonding pad area of the first side of the flexible circuit substrate. The wall at least partially surrounds the sensor integrated circuit.Type: GrantFiled: October 25, 2002Date of Patent: May 31, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Kok Wai Mui, Kim Heng Tan, Lan Chu Tan
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Publication number: 20040080037Abstract: An image sensor device is made using an ultra-thin substrate so that the overall device height is less than 1.0 mm. The image sensor includes a flexible circuit substrate having first and second opposing sides, the first side having a central area and an outer, bonding pad area including bonding pads. A sensor integrated circuit (IC) is attached to the central area of the first side of the circuit substrate. The IC has an active area and a peripheral bonding pad area including bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the circuit substrate bonding pads to electrically connect the IC and the circuit substrate. A wall having a first end with a step and a second end has its second end attached to an outer portion beyond the outer bonding pad area of the first side of the flexible circuit substrate. The wall at least partially surrounds the sensor integrated circuit.Type: ApplicationFiled: October 25, 2002Publication date: April 29, 2004Inventors: Chee Seng Foong, Kok Wai Mui, Kim Heng Tan, Lan Chu Tan
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Publication number: 20040065933Abstract: An image sensor device (10) has a transparent base carrier (12) and a circuit substrate (18) having a first side (20) attached to one planar side (14) of the base carrier (12). The substrate (18) includes a peripheral area (24) and a window area (26) that allows radiation to pass therethrough. A sensor integrated circuit (40) having an active area and a peripheral bonding pad area is connected to a second side (22) of the substrate (18) via flip chip bumps (42). Solder balls (46) are attached to an outer peripheral area of the second side (22) of the substrate (18). The substrate (18) provides for electrical interconnect between the solder balls (46) and the flip chip bumps (42). The overall device has a thickness of less than about 1.0 mm.Type: ApplicationFiled: October 8, 2002Publication date: April 8, 2004Inventors: Chee Seng Foong, Kok Wai Mui, Lan Chu Tan
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Publication number: 20030111720Abstract: An integrated circuit die (106) of a stacked multichip package (100) has a body (122) with a bottom surface (124) for being adhered to a surface of another integrated circuit die (104) of the stacked multichip package (100), and a top surface (126). The top surface (126) includes bonding pads (128). The body (122) also includes steps (130) extending along a periphery of the bottom surface (124) such that an area of the bottom surface (124) is less than an area of the top surface (126) and such that the die (106) has a T-shaped cross-section. When the die (106) is attached on top of another die (104), the steps (130) form a space for the wirebonds of the wires connecting the other die (104) to a carrier (102).Type: ApplicationFiled: December 18, 2001Publication date: June 19, 2003Inventors: Lan Chu Tan, Cheng Choi Yong, Chee Seng Foong, Ruzaini Bin Ibrahim