Patents by Inventor Chen Ma

Chen Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240066113
    Abstract: The present invention relates to the mRNA vaccine of coronavirus spike protein with deletion of glycosites in the receptor binding domain (RBD), the subunit 1 (S1) domain, or the subunit 2 (S2) domain, or a combination thereof. The vaccine elicits broadly protective immune responses coronavirus and variants thereof.
    Type: Application
    Filed: April 12, 2022
    Publication date: February 29, 2024
    Inventors: Chi-Huey WONG, Chung-Yi WU, Che MA, Chen-Yu FAN
  • Publication number: 20240074041
    Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 29, 2024
    Inventors: Gwo-Shyan Sheu, Kuo-Liang Huang, Hsin-Hao Huang, Pei-Wen Wang, Yu-Chen Ma
  • Patent number: 11916083
    Abstract: A display substrate has an active area which includes a photosensitive region with a light-transmitting channel. The display substrate includes a base, a pixel circuit layer, a first insulating layer and a conductive light-shielding layer. The pixel circuit layer includes pixel circuits and at least one pixel circuit includes a first thin film transistor and a second thin film transistor. The first insulating layer has a first via hole. The conductive light-shielding layer includes a conductive light-shielding pattern that has a first light-transmitting hole. Orthogonal projections of the first light-transmitting hole and of a gap region between the first thin film transistor and the second thin film transistor have a first overlapping region, which the light-transmitting channel penetrates. The conductive light-shielding pattern is coupled with a source electrode or a drain electrode of the first thin film transistor through the first via hole.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: February 27, 2024
    Assignees: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianbo Xian, Hongfei Cheng, Yongda Ma, Chen Xu, Xueguang Hao
  • Patent number: 11915379
    Abstract: The disclosure provides a display image adjustment method and an augmented reality display device. The display image adjustment method includes the following steps. Received image data is converted to a coordinate system of the augmented reality display device to obtain initial coordinate information. An initial image is provided to an active display region of the augmented reality display device based on the initial coordinate information. The initial coordinate information is adjusted in a virtual adjustment coordinate region to obtain adjusted coordinate information when an adjustment command is received. An adjusted image is provided to the active display region of the augmented reality display device based on the adjusted coordinate information. The display image adjustment method and the augmented reality display device proposed by the disclosure may adjust display content of the AR display device according to user's needs.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Shih-Min Wu, Yi-Fa Wang, Ping-Chen Ma
  • Publication number: 20240061759
    Abstract: An automatic test method and apparatus, an electronic device, and a storage medium are provided, which relate to the fields of the automatic test, the voice testing, the voice effect acceptance check, etc. The method includes: receiving a test task initiated by a visualization front-end; issuing the test task to a plurality of clients deployed; and scheduling execution of the test task for the plurality of clients, and feeding back obtained task execution results to the visualization front-end.
    Type: Application
    Filed: July 6, 2021
    Publication date: February 22, 2024
    Inventor: Chen Ma
  • Patent number: 11897695
    Abstract: A cabinet for goods storage and access is provided, including: at least one fixed shelf configured to store goods; a moving member located on a side of the fixed shelf; a controller configured to control the moving member to move along the side of the fixed shelf to place goods in the fixed shelf or extract goods from the fixed shelf; a cabinet body surrounding the fixed shelf and the moving member, wherein a first slot is disposed on the cabinet body and adjacent to a moving track of the moving member, wherein the controller is configured to control the first slot to be opened or closed; and a volume recognizer disposed adjacent to the first slot to recognize a volume of goods entering the first slot.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: February 13, 2024
    Assignee: CAINIAO SMART LOGISTICS HOLDING LIMITED
    Inventors: Yung-Chen Ma, Hongliang Zhou, Wei Lyu
  • Patent number: 11812554
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 7, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11606860
    Abstract: A flexible circuit board includes a flexible substrate, a chip and a patterned circuit layer. A surface of the flexible substrate is separated into a working area and a nonworking area according to a cutting line. The chip is disposed on the working area. The patterned circuit layer is disposed on the surface and includes signal transmission wires and bypass wires, the bypass wires are not electrically connected to the chip. Each of the bypass wires includes a bypass transmission portion located on the working area and an anti-peeling portion located on the nonworking area. A blank area exists between the anti-peeling area and the bypass transmission portion, and the cutting line passes through the blank area. A distance between 100 um and 400 um exists from the anti-peeling portion to the cutting line.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 14, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Gwo-Shyan Sheu, Hsin-Hao Huang, Yu-Chen Ma, Chia-Hsin Yen
  • Patent number: 11581283
    Abstract: A flip chip package includes a circuit board, a chip and a solder layer. The chip is mounted on an inner bonding area of the circuit board. The solder layer is located between the circuit board and the chip for bonding bumps to inner leads and a T-shaped circuit unit is on the inner bonding area. The T-shaped circuit unit has a main part, a connection part, and a branch part. The connection part is connected to the main and branch parts, respectively. The main part extends along a lateral direction and the branch part extends outwardly along a longitudinal direction. The connection part is narrower than the main part in width so as to inhibit solder shorts caused by solder overflow on the branch part.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 14, 2023
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Publication number: 20230044345
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a circuit layer, a flip-chip element and an anti-stress circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. Bonding circuits and transmission circuits of the circuit layer are disposed on the chip mounting area and the circuit area respectively. The flip-chip element is disposed on the chip mounting area and includes bumps and a chip having a long side margin and conductive pads, the bumps are provided to connect the conductive pads and the bonding circuits. Anti-stress circuits of the anti-stress circuit layer are disposed on the chip mounting area and parallel to the long side margin of the chip, and the bumps are located between the anti-stress circuits and the long side margin of the chip.
    Type: Application
    Filed: June 24, 2022
    Publication date: February 9, 2023
    Inventors: Yu-Chen Ma, Pei-Wen Wang, Hsin-Hao Huang, Gwo-Shyan Sheu
  • Publication number: 20220370960
    Abstract: Disclosed herein are membranes comprising: porous substrate; and two or more graphene oxide (GO) sheets disposed on the porous substrate, each GO layer comprising a plurality of GO flakes, each GO flake comprising a planar graphene structure with oxygen moieties extending therefrom, wherein the membrane, when a pressure from 10 bar to 50 bar of transmembrane pressure is applied from 1 hour to 48 hours, has an aqueous flux wherein the aqueous flux changes by 5% or less while the pressure is applied. The membranes can also include an intercalating agent disposed between the two or more GO sheets, the intercalating agent interacting with each GO sheet, wherein the intercalating agent provides a non-covalent stabilization of the two or more GO sheets. Also disclosed herein are methods of making and using the same and systems for implementing the same.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 24, 2022
    Inventors: Sankar Nair, Chen Ma, Meisha Shofner, Scott Sinquefield, Zhongzhen Wang
  • Publication number: 20220366652
    Abstract: The disclosure provides a display image adjustment method and an augmented reality display device. The display image adjustment method includes the following steps. Received image data is converted to a coordinate system of the augmented reality display device to obtain initial coordinate information. An initial image is provided to an active display region of the augmented reality display device based on the initial coordinate information. The initial coordinate information is adjusted in a virtual adjustment coordinate region to obtain adjusted coordinate information when an adjustment command is received. An adjusted image is provided to the active display region of the augmented reality display device based on the adjusted coordinate information. The display image adjustment method and the augmented reality display device proposed by the disclosure may adjust display content of the AR display device according to user's needs.
    Type: Application
    Filed: April 14, 2022
    Publication date: November 17, 2022
    Applicant: Coretronic Corporation
    Inventors: Shih-Min Wu, Yi-Fa Wang, Ping-Chen Ma
  • Publication number: 20220342220
    Abstract: A wearable device and a method for adjusting a display state based on an environment are provided. The method is adapted for the wearable device. The method includes: capturing an environmental image; when determining that there is a specific object in the environmental image, determining a display mode of a display circuit based on the specific object; and controlling the display circuit to be adjusted to a display state corresponding to the display mode.
    Type: Application
    Filed: March 25, 2022
    Publication date: October 27, 2022
    Applicant: Coretronic Corporation
    Inventors: Shih-Min Wu, Yi-Fa Wang, Ping-Chen Ma
  • Publication number: 20220253688
    Abstract: Recommendation system for processing an input dataset that identifies a set of users, a set of items, and user-item interaction data. A plurality of unique triplets are identified based on the input dataset, wherein each triplet includes: a positive user-item pair; and a negative user-item pair. Over a plurality of training iterations system parameters are learned, including (i) a set of model embeddings for generating respective user-item relevance scores for the positive user-item pairs and the negative user-item pairs; and (ii) weight parameters for each of the triplets. The learning is configured to jointly optimize the model embeddings and the weight parameters to reach a learning objective that is based on weighted difference values determined for the triplets.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 11, 2022
    Inventors: Haolun WU, Chen MA, Yingxue ZHANG
  • Publication number: 20220253722
    Abstract: A recommendation system (RS) for processing an input dataset that identifies a set of users, a set of items, and user-item interaction data about historic interactions between users in the set of users and items in the set of items. The RS is configured to: generate, based on a user-item interaction dataset, a user-user similarity dataset and an item-item similarity dataset, filter the user-user similarity dataset based on a user similarity threshold vector that includes a respective user similarity threshold value for each user, filter the item-item similarity dataset based on an item similarity threshold vector including a respective item similarity threshold value for each item generate a set of user neighbour embeddings based on the filtered user-user similarity dataset, and generating a set of item neighbour embeddings based on the filtered item-item similarity dataset.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 11, 2022
    Inventors: Haolun WU, Chen MA, Yingxue ZHANG, Mark COATES
  • Publication number: 20220225496
    Abstract: A flexible circuit board includes a flexible substrate, a chip and a patterned circuit layer. A surface of the flexible substrate is separated into a working area and a nonworking area according to a cutting line. The chip is disposed on the working area. The patterned circuit layer is disposed on the surface and includes signal transmission wires and bypass wires, the bypass wires are not electrically connected to the chip. Each of the bypass wires includes a bypass transmission portion located on the working area and an anti-peeling portion located on the nonworking area. A blank area exists between the anti-peeling area and the bypass transmission portion, and the cutting line passes through the blank area. A distance between 100 um and 400 um exists from the anti-peeling portion to the cutting line.
    Type: Application
    Filed: October 19, 2021
    Publication date: July 14, 2022
    Inventors: Gwo-Shyan Sheu, Hsin-Hao Huang, Yu-Chen Ma, Chia-Hsin Yen
  • Patent number: 11322437
    Abstract: A flip chip interconnection including a circuit board is disclosed. The circuit board includes a substrate, inner leads, a T-shaped circuit line and a dummy pattern. The inner leads, the T-shaped circuit line and the dummy pattern are located on an inner bonding area of the substrate. The T-shaped circuit line includes a main segment, a branch segment and a connection segment that is connected to the main segment and the branch segment. The main segment and the branch segment are extended along a lateral direction and a longitudinal direction, respectively. The dummy pattern is located between the connection segment and the inner leads.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 3, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Patent number: 11309238
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate, the circuit area surrounds the chip mounting area. The chip is mounted on the chip mounting area of the top surface and includes a bump. The circuit layer is disposed on the top surface. A connection portion of the circuit layer extends across a first side of the chip mounting area and into the chip mounting area. A transmission portion of the circuit layer is located on the circuit area and electrically connected to the connection portion. A stress release portion of the circuit layer is located between the transmission portion and a second side of the chip mounting area and is a comb-shaped structure.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 19, 2022
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu
  • Publication number: 20220111008
    Abstract: Provided is use of IL-15 protein complex joint PD-L1 antibody for treating tumor diseases.
    Type: Application
    Filed: December 12, 2019
    Publication date: April 14, 2022
    Inventors: Xing Sun, Chen Ma, Changyong Yang, Cheng Liao, Lianshan Zhang, Jianjun Zou, Wei Shi, Yuanyuan Du, Yujie Zhou
  • Publication number: 20220104354
    Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.
    Type: Application
    Filed: April 12, 2021
    Publication date: March 31, 2022
    Inventors: Yu-Chen Ma, Hsin-Hao Huang, Wen-Fu Chou, Gwo-Shyan Sheu