Patents by Inventor Chen-Nan Yeh
Chen-Nan Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150129990Abstract: A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Sey-Ping SUN, Tsung-Lin LEE, Chin-Hsiang LIN, Chih-Hao CHANG, Chen-Nan YEH, Chao-An JONG
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Patent number: 8957477Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.Type: GrantFiled: October 13, 2011Date of Patent: February 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Yi Lee, Shih-Ting Hung, Chen-Nan Yeh, Chen-Hua Yu
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Patent number: 8946828Abstract: A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.Type: GrantFiled: February 9, 2010Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sey-Ping Sun, Tsung-Lin Lee, Chin-Hsiang Lin, Chih-Hao Chang, Chen-Nan Yeh, Chao-An Jong
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Patent number: 8912602Abstract: A Fin field effect transistor includes a fin disposed over a substrate. A gate is disposed over a channel portion of the fin. A source region is disposed at a first end of the fin. A drain region is disposed at a second end of the fin. The source region and the drain region are spaced from the substrate by at least one air gap.Type: GrantFiled: April 12, 2010Date of Patent: December 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Rung Hsu, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 8883597Abstract: The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.Type: GrantFiled: July 31, 2007Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Yu-Rang Hsu, Ding-Yuan Chen
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Publication number: 20140070318Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.Type: ApplicationFiled: November 14, 2013Publication date: March 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Yu-Rung Hsu, Chen-Nan Yeh, Cheng-Hung Chang
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Patent number: 8617948Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.Type: GrantFiled: May 9, 2011Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yu-Rung Hsu, Chen-Nan Yeh, Cheng-Hung Chang
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Patent number: 8450200Abstract: A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.Type: GrantFiled: December 20, 2010Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan, Jye-Yen Cheng
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Publication number: 20120299110Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.Type: ApplicationFiled: July 31, 2012Publication date: November 29, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Ting Hung, Cheng-Hung Chang, Chen-Yi Lee, Chen-Nan Yeh, Chen-Hua Yu
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Patent number: 8263462Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.Type: GrantFiled: December 31, 2008Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Hung, Cheng-Hung Chang, Chen-Yi Lee, Chen-Nan Yeh, Chen-Hua Yu
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Publication number: 20120211807Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.Type: ApplicationFiled: February 10, 2012Publication date: August 23, 2012Applicant: Taiwan Semiconductor Manufacturing Comapny, Ltd.Inventors: Chen-Hua YU, Cheng-Hung CHANG, Chen-Nan YEH, Yu-Rung HSU
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Publication number: 20120094464Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.Type: ApplicationFiled: December 23, 2011Publication date: April 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen
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Publication number: 20120083107Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.Type: ApplicationFiled: December 8, 2011Publication date: April 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 8143114Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.Type: GrantFiled: February 15, 2011Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Chen-Nan Yeh, Yu-Rung Hsu
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Patent number: 8110890Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.Type: GrantFiled: June 5, 2007Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen
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Publication number: 20120025313Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.Type: ApplicationFiled: October 13, 2011Publication date: February 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Yi Lee, Shih-Ting Hung, Chen-Nan Yeh, Chen-Hua Yu
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Patent number: 8106459Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.Type: GrantFiled: May 6, 2008Date of Patent: January 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh
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Patent number: 8101994Abstract: A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.Type: GrantFiled: October 26, 2010Date of Patent: January 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Nan Yeh, Yu-Rung Hsu
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Patent number: 8048723Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.Type: GrantFiled: December 5, 2008Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Yi Lee, Shih-Ting Hung, Chen-Nan Yeh, Chen-Hua Yu
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Publication number: 20110223735Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.Type: ApplicationFiled: May 9, 2011Publication date: September 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: CHEN-HUA YU, YU-RUNG HSU, CHEN-NAN YEH, CHENG-HUNG CHANG