Patents by Inventor Chen Tseng

Chen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118202
    Abstract: A rapid fresh digital-pathology (RFP) method for assessing an excised unfixed biological specimen stained with hematoxylin (H) or eosin (E) or both hematoxylin and eosin (HE) staining dyes. The RFP method is assisted by a rapid tissue staining (RTS) procedure which is performed on the excised unfixed biological specimen, involving a short fixation; an H-staining; a rinsing; a bluing; an E-staining; a rinsing; and finally, a covering of a stained specimen with a coverslip. The RFP method is further assisted by a multimodal nonlinear optical laser-raster-scanning approach to provide with a nonlinear multi-harmonic generation and/or a nonlinear multi-photon excitation fluorescence signal(s) for multichannel digitization and real-time digital display of H- or E- or HE-specific histopathological features while providing a centimeter-scale imaging area, a submicron digital resolution, and a sustained effective data throughput of at least 500 Megabits per second (Mbps).
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Chi-Kuang Sun, Bhaskar Jyoti Borah, Yao-Chen Tseng
  • Publication number: 20240120854
    Abstract: A triboelectric nanogenerating device is configured for providing an electric power to an electronic device and the triboelectric nanogenerating device includes at least one scaly triboelectric membrane configured for providing the electric power to the electronic device by frictional electrification. The at least one scaly triboelectric membrane includes a keratin and a polyvinyl alcohol, the at least one scaly triboelectric membrane has a first triboelectric surface, and the first triboelectric surface of the at least one scaly triboelectric membrane includes a plurality of scaly layers. Each of the scaly layers is arranged in order and extends along an orienting direction. A distal end of each of the scaly layers has a plurality of saw-tooth structures.
    Type: Application
    Filed: February 6, 2023
    Publication date: April 11, 2024
    Inventors: Zong-Hong Lin, Ming-Zheng Huang, Hsuan-Yu Yeh, An-Rong Chen, Yao-Hsuan Tseng
  • Publication number: 20240093416
    Abstract: A sewing machine includes a main body and a quick release needle plate module. The main body includes a base seat having an inner frame, and an outer case that is mounted to the inner frame and that defines an accommodating compartment. The quick release needle plate module includes a catch member, and a needle plate that covers the accommodating compartment, that is detachably pivoted to a rear section of the inner frame, and that engages the catch member. The quick release needle plate module further includes a press member inserted through the outer case and the inner frame, and operable to push the catch member to disengage the catch member. The needle plate has a plate body that covers the accommodating compartment, and a resilient member mounted between the inner frame and the plate body for driving pivot action of the plate body away from the inner frame.
    Type: Application
    Filed: January 20, 2023
    Publication date: March 21, 2024
    Applicant: ZENG HSING INDUSTRIAL CO., LTD.
    Inventors: Kun-Lung HSU, Ming-Ta LEE, Wei-Chen CHEN, Po-Hsien TSENG
  • Publication number: 20240090564
    Abstract: Features relating to a vaporizer body are provided. The vaporizer body may include an outer shell that includes an inner region defined by an outer shell sidewall. A support structure is configured to fit within the inner region of the outer shell. The support structure includes a storage region defined by a top support structure, a bottom support structure, a bottom cap, and a gasket. An integrated board assembly is configured to fit within the storage region of the support structure. The integrated board assembly may include a printed circuit board assembly formed of multiple layers that form a rigid structure and that include an inner, flexible layer. A first antenna is integrated at a proximal end of the flexible layer, and a second antenna is integrated at a distal end of the flexible layer.
    Type: Application
    Filed: April 24, 2023
    Publication date: March 21, 2024
    Inventors: Joshua Fu, Christopher Loental, Marko Markovic, Alexander Weiss, Alexander Ringrose, David Carlberg, Robyn Nariyoshi, Devin Spratt, Nicholas J. Hatton, Yen Jen Chang, Chen Yu Li, Barry Tseng, Prince Wang, Thomas Germann, Andreas Schaefer
  • Publication number: 20240098833
    Abstract: A method for mobility enhancement in wireless communication systems is provided. The method is performed by a User Equipment (UE) configured with a first Small Data Transmission (SDT) configuration by a first cell. The method includes receiving a Radio Resource Control (RRC) release message including a suspend configuration from the first cell; transitioning to an RRC INACTIVE state in response to receiving the RRC release message; receiving, in the RRC INACTIVE state, a System Information Block Type 1 (SIB1) including a second SDT configuration from a second cell; camping on the second cell in response to receiving the SIB1 from the second cell; and while the UE is camping on the second cell, refraining from using the first SDT configuration to initiate an SDT procedure associated with the second cell in a case that the UE does not support performing the SDT procedure associated with the second cell.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 21, 2024
    Inventors: YUNG-LAN TSENG, YEN-HUA LI, HAI-HAN WANG, HUNG-CHEN CHEN
  • Patent number: 11937327
    Abstract: A user equipment (UE) and a method performed by the UE are provided. The method includes transitioning from a radio resource control (RRC) inactive (RRC_INACTIVE) state to an RRC idle (RRC_IDLE) state upon determining that the UE has failed to find a suitable cell and camped on an acceptable cell; and discarding a radio access network (RAN) notification area (RNA) configuration that comprises at least one of a list of tracking area identities (IDs) or a list of RAN area IDs in response to the transitioning from the RRC_INACTIVE state to the RRC_IDLE state. The acceptable cell fulfills a minimum set of requirements to initiate an emergency call and to receive one or more Earthquake & Tsunami Warning System (ETWS) and Commercial Mobile Alert System (CMAS) notifications. The suitable cell provides normal services. The acceptable cell provides limited services.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: March 19, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Mei-Ju Shih, Yung-Lan Tseng, Hung-Chen Chen, Chie-Ming Chou
  • Patent number: 11923378
    Abstract: The present disclosure provides an electronic device including a substrate, a common electrode, and a plurality of pixels. The common electrode is disposed on the substrate. The pixels are disposed on the substrate, and at least one of the pixels includes a thin film transistor, a first electrode, a second electrode, and an auxiliary electrode. The first electrode is electrically connected to the thin film transistor. The auxiliary electrode is partially overlapped with the first electrode in a top view direction of the electronic device. The auxiliary electrode is electrically connected to the common electrode and electrically isolated from the first electrode, and the first electrode and the auxiliary electrode have a minimum distance less than a minimum distance between the first electrode and the common electrode.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: March 5, 2024
    Assignee: InnoLux Corporation
    Inventors: Chi-Lun Kao, Ker-Yih Kao, Ming-Chun Tseng, Kung-Chen Kuo
  • Patent number: 11921325
    Abstract: A semiconductor device is provided. The semiconductor device includes a waveguide over a substrate. The semiconductor device includes a first dielectric structure over the substrate, wherein a portion of the waveguide is in the first dielectric structure. The semiconductor device includes a second dielectric structure under the waveguide, wherein a first sidewall of the second dielectric structure is adjacent a first sidewall of the substrate.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Chen Chen, Lee-Chuan Tseng, Shih-Wei Lin
  • Patent number: 11923466
    Abstract: A photodetector with an integrated reflective grating structure includes a substrate, an active layer disposed on the substrate, and a grating structure disposed between the substrate and the active layer. A first doped region is formed on the substrate at a location near the grating structure. A second doped region is formed on a surface of the active layer away from the grating structure. The doping type of the second doped region is different from that of the first doped region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 5, 2024
    Assignee: INNOLIGHT TECHNOLOGY (SUZHOU) LTD.
    Inventors: Chih-Kuo Tseng, Guoliang Chen, Xiaoyao Li, Yuzhou Sun, Yue Xiao
  • Patent number: 11924698
    Abstract: A method for a user equipment (UE) for cell selection while the UE is in a radio resource control (RRC) Inactive state is provided. The method receives, via control signaling, a configuration indicating a target frequency carrier and a corresponding target core network (CN) type. The method then causes the UE to transition from an RRC Connected state to the RRC Inactive state based on the received configuration. While the UE is in the RRC Inactive state, the method selects a suitable cell among a plurality of suitable cells that are associated with the target frequency carrier. The method selects the suitable cell irrespective of the received target CN type.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 5, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Yung-Lan Tseng, Mei-Ju Shih, Hung-Chen Chen
  • Patent number: 11917445
    Abstract: A method performed by a BS for CHO is provided. The method includes transmitting a CHO command to a UE, the CHO command including a CHO command ID and a measurement ID associated with the CHO command ID; causing the UE to execute the CHO command to handover to a target BS when a trigger condition associated with the measurement ID is fulfilled; causing the UE to forgo transmitting the measurement report during the execution of the CHO command despite the UE being configured, via a report configuration associated with the measurement ID, to transmit the measurement report; transmitting, to the UE, a message that causes the UE to remove the CHO command; and after transmitting the message to the UE, determining that the report configuration is removed by the UE without transmitting, to the UE, an instruction to remove the report configuration.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: February 27, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Hung-Chen Chen, Yung-Lan Tseng, Mei-Ju Shih, Chie-Ming Chou
  • Publication number: 20240048740
    Abstract: An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.
    Type: Application
    Filed: April 17, 2023
    Publication date: February 8, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Chen Tseng, Po-Hsien Wu
  • Publication number: 20240048734
    Abstract: An image processing method includes receiving an image frame, retrieving luminance information and chrominance information from the image frame, respectively, encoding the luminance information to generate an encoded luminance frame, encoding the chrominance information to generate an encoded chrominance frame, writing the encoded luminance frame to a first memory portion of a memory, and writing the encoded chrominance frame to a second memory portion of the memory. The image processing method further includes reading the encoded luminance frame from the first memory portion and decoding the encoded luminance frame to generate decoded luminance information, and reading the encoded chrominance frame from the second memory portion and decoding the encoded chrominance frame to generate decoded chrominance information.
    Type: Application
    Filed: April 17, 2023
    Publication date: February 8, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Po-Hsien Wu, Yi-Chen Tseng
  • Patent number: 11880140
    Abstract: The present disclosure, in some embodiments, relates to a method of developing a photosensitive material. The method includes forming a photosensitive material over a substrate. The photosensitive material is exposed to electromagnetic radiation focused at a plurality of different heights over the substrate. The plurality of different heights are vertically separated from one another and are disposed within the photosensitive material along a vertical path that extends in a direction perpendicular to an upper surface of the photosensitive material. The photosensitive material is developed to remove a soluble region.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: January 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Patent number: 11862594
    Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20230418560
    Abstract: The present invention discloses a computation circuit. Each of a first and a second term computation circuits includes higher bit computation circuits, a lowest bit computation circuit and a first adder. Each of the higher bit computation circuits left-shifts a multiplier, outputs the effective shifted multiplier having a sign determined and further performs left-shifts without performing 2's complement computation to generate a higher bit computation result. The lowest bit computation circuit outputs the effective multiplier having the sign determined to generate a lowest bit computation result. The first adder adds the bit computation results to generate a term computation result. The third term computation circuit outputs an effective addend having the sign determined and adds the addend to the summation of a number of 2's complement to generate a third term computation result. The second adder adds the term computation results and the third term computation result to generate a total computation result.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 28, 2023
    Inventors: SZU-CHUN CHANG, YI-CHEN TSENG
  • Patent number: 11854927
    Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230386955
    Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230386906
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230308687
    Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 28, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Hsu-Jung Tung, Chi-Wang Chai, Weimin Zeng, Yi-Chen Tseng