Patents by Inventor Chen Tseng

Chen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282558
    Abstract: A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Sih-Hao Liao, Wei-Chih Chen, Hung-Chun Cho, Ting-Chen Tseng, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20230075146
    Abstract: The present disclosure, in some embodiments, relates to a method of developing a photosensitive material. The method includes forming a photosensitive material over a substrate. The photosensitive material is exposed to electromagnetic radiation focused at a plurality of different heights over the substrate. The plurality of different heights are vertically separated from one another and are disposed within the photosensitive material along a vertical path that extends in a direction perpendicular to an upper surface of the photosensitive material. The photosensitive material is developed to remove a soluble region.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 9, 2023
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Publication number: 20230063181
    Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11520237
    Abstract: The present disclosure, in some embodiments, relates to a photolithography tool. The photolithography tool includes a source configured to generate electromagnetic radiation. A dynamic focal system is configured to provide the electromagnetic radiation to a plurality of different vertical positions over a substrate stage. The plurality of different vertical positions include a first position having a first depth of focus and a second position having a second depth of focus that is below the first depth of focus and that vertically overlaps the first depth of focus.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Publication number: 20220359446
    Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20220310467
    Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 29, 2022
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11361564
    Abstract: An image integrated printing system includes an image capturing device, a host device, and a printing device. The image capturing device is for capturing an image of an object. The host device is electrically connected to the image capturing device and includes a storage unit, a recognition unit, and a processing unit. The storage unit is for storing the image transmitted from the image capturing device and a form. The recognition unit is for recognizing a field corresponding to the image from the form. The processing unit is electrically connected to the storage unit and the recognition unit and for combining the image with the field corresponding to the image to generate an output file. The printing device is electrically connected to the host device and for printing the output file.
    Type: Grant
    Filed: January 1, 2019
    Date of Patent: June 14, 2022
    Assignee: AVISION INC.
    Inventors: Chen-Chang Li, Chun-Chieh Liao, Shao-Lan Sheng, Xiang-Chi Lee, Cheng-Chen Tseng
  • Publication number: 20220139774
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20220124930
    Abstract: An apparatus and method simulates cable routing for determining signal integrity between electronic components within a computer chassis. The apparatus includes a base plate simulating a computer chassis base. The base plate includes a top surface. A plurality of reconfigurable mounting fixtures each allow temporary mounting of a printed circuit board assembly (PCBA) to a respective reconfigurable mounting fixture. The plurality of reconfigurable mounting fixtures is temporarily mountable anywhere on the top surface of the base plate. A cable including a first end connector allows a connection to a first PCBA, and a second end connector allows a connection to a second PCBA.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 21, 2022
    Inventors: Yaw-Tzorng TSORNG, Chen-Chien KUO, Chen TSENG
  • Patent number: 11274911
    Abstract: A cable measuring tool includes a first end portion and a second end portion. The first end portion includes a first rounded edge and a cutaway. The cutaway is configured to fit at least a half of a cable having a maximum diameter. The first rounded edge has a radius greater than the maximum diameter of the cable. The second end portion is opposite from the first end portion. The second end portion includes a second edge. The first rounded edge of the first end portion and the second edge of the second end portion define a length of the cable measuring tool.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: March 15, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chun Chang, Chen Tseng, Cheng-Hsiang Huang, Chih-Hung Yang, I-Hui Chen
  • Publication number: 20220071344
    Abstract: A sole structure includes: an anti-skid layer, a rigid layer, an elastic piece and a soft layer which are superimposed upon one another. With the characteristic of the elastic piece being elastically deformable, a rebounding force can be produced to act on the foot to stimulate the ligaments and muscles of the foot, which consequently corrects flatfootedness.
    Type: Application
    Filed: November 18, 2021
    Publication date: March 10, 2022
    Inventor: Yi-Chen TSENG
  • Publication number: 20220074726
    Abstract: A cable measuring tool includes a first end portion and a second end portion. The first end portion includes a first rounded edge and a cutaway. The cutaway is configured to fit at least a half of a cable having a maximum diameter. The first rounded edge has a radius greater than the maximum diameter of the cable. The second end portion is opposite from the first end portion. The second end portion includes a second edge. The first rounded edge of the first end portion and the second edge of the second end portion define a length of the cable measuring tool.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 10, 2022
    Inventors: Chun CHANG, Chen TSENG, Cheng-Hsiang HUANG, Chih-Hung YANG, I-Hui CHEN
  • Patent number: 11227795
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20210255549
    Abstract: The present disclosure, in some embodiments, relates to a photolithography tool. The photolithography tool includes a source configured to generate electromagnetic radiation. A dynamic focal system is configured to provide the electromagnetic radiation to a plurality of different vertical positions over a substrate stage. The plurality of different vertical positions include a first position having a first depth of focus and a second position having a second depth of focus that is below the first depth of focus and that vertically overlaps the first depth of focus.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Patent number: 11087427
    Abstract: A method for dynamically limiting a memory bandwidth of a graphics processing unit (GPU) is applicable to a bandwidth-limited system. The bandwidth-limited system includes an audio/video decoder and a GPU. The method includes detecting a plurality of decoding times of a plurality of frames of an audio/video decoded by an audio/video decoder, and adjusting a max grant amount of a memory bandwidth of a GPU according to the plurality of decoding times of the plurality of frames and a target time. Therefore, in the case where the total memory bandwidth is limited, the memory bandwidth of the GPU is limited by the performance of the corresponding audio/video decoder such that, during audio/video playback, the effect of audio/video playback can be prevented from being affected and at the same time a better graphical user interface can be provided.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 10, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Chen Tseng, Ming-Yang Tseng
  • Publication number: 20210225699
    Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Ting-Chen Tseng, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20210193605
    Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11003089
    Abstract: The present disclosure, in some embodiments, relates to a method of performing a photolithography process. The method includes forming a photosensitive material over a substantially flat upper surface of a substrate. The substantially flat upper surface of the substrate extends between opposing sides of the substrate. The photosensitive material is exposed to electromagnetic radiation at a plurality of depths of focus that are centered at different heights over the substrate. The photosensitive material is developed to remove a part of the photosensitive material.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Patent number: 10937968
    Abstract: Provided are a novel compound and an organic electronic device using the same. The novel compound is represented by Formula (I): wherein n1, n2, m1, m2 and m3 are each an integer, the sum of n1 and n2 is 2 or 3; L1, L2 and L3 are each an arylene group; R1 and R2 are each selected from the group consisting of: H, D, an alkyl group, and an aryl group; G is selected from the group consisting of: H, D, —N(Z3)(Z4) group, an alkyl group, an alkenyl group, an alkynyl group, a cycloalkyl group, a heterocycloalkyl group, an aryl group, and a heteroaryl group; and Z1 to Z4 are each selected from the group consisting of: an alkyl group, an alkenyl group, an alkynyl group, a cycloalkyl group, a heterocycloalkyl group, an aryl group, and a heteroaryl group.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 2, 2021
    Assignee: SHANGHAI NICHEM FINE CHEMICAL CO., LTD.
    Inventors: Hui-Ling Wu, Po-Chen Tseng, Shwu-Ju Shieh, Chi-Chung Chen
  • Publication number: 20200310501
    Abstract: A hard disk drive (HDD) carrier bracket for use in mounting a hard disk drive (HDD) in a chassis via a HDD tray includes a first frame member and a second frame member. The second frame member is coupled to the first frame member such that the first and second frame members are moveable relative to one another, between an extended position and a collapsed position. The HDD carrier bracket is installable in the HDD tray without tools. The HDD tray is installable in the chassis without tools.
    Type: Application
    Filed: May 29, 2019
    Publication date: October 1, 2020
    Inventors: Yaw-Tzorng TSORNG, Chun CHANG, Chen TSENG