Abstract: A data model training method and apparatus are provided. The method includes receiving data subsets from a plurality of subnodes and performing data convergence based on the plurality of data subsets to obtain a first data set. A first data model and at least one of the first data set or a subset of the first data set are sent to a first subnode, where an artificial intelligence (AI) algorithm is configured for the first subnode. A second data model is received from the first subnode, where the second data model is obtained by training the first data model based on the first data set or the subset of the first data set. The first data model is updated based on the second data model to obtain a target data model, the target data model is sent to the plurality of subnodes.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes an interposer, chips, and warpage adjustment structures, wherein the interposer includes a first surface and a second surface opposite thereto, and the chips are electrically connected to the first surface of the interposer; the warpage adjustment structures are symmetrically distributed with respect to a center of the first surface; and each of the warpage adjustment structures include a warpage adjustment piece and/or a cavity filled with a plastic packaging material, the warpage adjustment piece is disposed on the first surface, and the cavity is located outside conducting structures and sinks inward along the first surface. By cooperation between the warpage adjustment pieces and the cavities filled with the plastic packaging material, the warpage of the interposer in horizontal and vertical directions can be reduced.

Abstract: The present application provides a pixel structure, an image sensor, a device, an image processing method and a control method.

Abstract: A display substrate is provided. The display substrate includes a base substrate including a display region and a peripheral region, and a first scan driving circuit, a second scan driving circuit and a first power line arranged in sequence, and a first shielding layer and a second shielding layer sequentially arranged on a side of the second scan driving circuit away from the base substrate; the first shielding layer covers at least one transistor in the second scan driving circuit, and the second shielding layer covers at least one transistor of transistors in the second scan driving circuit except the at least one transistor covered by the first shielding layer; and the second shielding layer is also on a side of the first scan driving circuit away from the base substrate, and the second shielding layer covers at least one transistor in the first scan driving circuit.

Abstract: A transmitter for inductive charging of a device comprising a receiver is provided. The transmitter includes a set of coils, including a first coil having a first turn and a second turn. The first turn and the second turn are adjacent. The first turn has the first sense and the second turn has the second sense, opposed to the first sense; whereby, in use, current flows through the first turn and the second turn in opposed senses.

Abstract: A back-contacting solar cell includes: a silicon substrate (1), wherein a shadow face of the silicon substrate (1) is delimited into a first region and a second region (2), and the second region (2) is doped to form a second-charge-carrier collecting end; a metal-chalcogen-compound layer (4), wherein the metal-chalcogen-compound layer (4) is deposited within at least the first region of the silicon substrate (1), and a region of the metal-chalcogen-compound layer (4) that corresponds to the first region forms a first-charge-carrier collecting end; a first electrode (5), wherein the first electrode (5) is correspondingly provided on the first-charge-carrier collecting end; and a second electrode (6), wherein the second electrode (6) is correspondingly provided within a region that corresponds to the second region (2). The collection and transferring of the first charge carrier are realized by using the first-charge-carrier collecting end.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: A tandem cell is provided in the present disclosure, which relates to the technical field of photovoltaics, so as to form a functional layer with high film ordering on a bottom cell, thereby improving photoelectric conversion efficiency of the tandem cell. The tandem cell includes: a bottom cell with a textured surface; a hole transport layer formed on the textured surface of the bottom cell; a second ordered induction layer and a perovskite absorption layer formed on the hole transport layer, the second ordered induction layer being located between the hole transport layer and the perovskite absorption layer; and a transparent conductive layer formed on the perovskite absorption layer. An inducing material contained in the second ordered induction layer is organic ammonium salt or inorganic lead compound. The tandem cell according to the present disclosure is a tandem cell with a perovskite solar cell as a top cell.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package and an upper package; wherein the lower package includes a prefabricated interconnected silicon core stack structure which includes a silicon interconnection layer, and the silicon interconnection layer includes a first surface and a second surface; a back-end redistribution stack layer and a first prefabricated redistribution stack layer are stacked on the first surface and in electrical connection; a passivation layer is disposed on the second surface; the silicon interconnection layer includes a silicon substrate and several first prefabricated conductive pillars, each first prefabricated conductive pillar includes a first end and a second end, the first end is exposed from the first surface, and the second end is exposed from a side of the passivation layer; and the upper package is disposed above the first prefabricated redistribution stack layer.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package, an upper package and a first redistribution stack layer disposed between the lower package and the upper package, wherein the first redistribution stack layer is electrically connected to the lower package and the upper package; the lower package includes a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; and the minimum line width/line spacing of the first redistribution stack layer is less than the minimum line width/line spacing of the prefabricated substrate. The lower package includes the prefabricated substrate and the first redistribution stack layer is disposed above the prefabricated substrate and has the minimum line width/line spacing less than that of the prefabricated substrate, so that more chips and/or device packages are integrated in the packaging structure.

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes: a lower package, an upper package disposed above the lower package, and a first redistribution stack layer that is disposed between the lower package and the upper package and is electrically connected to the lower package and the upper package. The lower package includes a first prefabricated redistribution stack layer and a first plastic packaging layer surrounding the first prefabricated redistribution stack layer. A minimum line width and line spacing of at least one first prefabricated conductive layer in the first prefabricated redistribution stack layer is less than a minimum line width and line spacing of at least one first conductive layer in the first redistribution stack layer.

Abstract: The present invention relates to a magnetic recording medium including a substrate; an underlayer laminated upon the substrate; and a magnetic layer laminated upon the underlayer, wherein the underlayer includes a first underlayer containing a compound represented by a following general formula: MgO(1-X), where X is within a range of 0.07 to 0.25, the magnetic layer includes a first magnetic layer containing an alloy having a L10 structure, and the alloy having the L10 structure includes B, and the first underlayer is in contact with the first magnetic layer.

Abstract: A display panel is provided. The display panel has a display region and a peripheral region, the peripheral region includes a first peripheral region, a bending region, and a second peripheral region. The display panel includes a base substrate, a driving circuit layer, an organic structure, and an encapsulation layer; the organic structure includes a first organic structure and a second organic structure, the first organic structure is in the first peripheral region, and the second organic structure includes a first portion in the first peripheral region and a second portion in the bending region; the encapsulation layer partially overlaps with the second organic structure, a portion of the encapsulation layer which overlaps with the second organic structure includes a first encapsulation portion and a second encapsulation portion; an average thickness of the first encapsulation portion is greater than an average thickness of the second encapsulation portion.

Abstract: A display panel and a display device are provided, since a plurality of source ICs (01) are arranged, a large-sized display panel is driven, and since the plurality of source ICs (01) are scattered around a display area (A) along the tangential directions of the edge of the display area (A), that is, the source ICs (01) are distributed according to the shape of the display panel, a distance between the source ICs (01) and the display area (A) is shortened, and thus a narrow bezel design of the display panel is facilitated.

Abstract: A display panel and a display device are provided.

Abstract: This application provides a communication method and apparatus. The method may include: A first communication apparatus receives configuration information of a first neural network; the first communication apparatus determines the first neural network based on the configuration information of the first neural network; the first communication apparatus obtains first channel information based on channel information obtained through measurement and the first neural network, where a data amount of the first channel information is less than a data amount of the channel information obtained through measurement; and the first communication apparatus sends the first channel information, where the first channel information is used to obtain second channel information by using a second neural network, and the second channel information is used for data transmission.

Abstract: A display substrate is provided. The display substrate includes a base substrate including a display region and a peripheral region, and a gate scan driving circuit, a light-emitting control scan driving circuit, and a first power line, the gate scan driving circuit includes a first stabilizing capacitor, a first electrode plate of the first stabilizing capacitor is electrically connected to the output terminal of the gate scan driving circuit; and the light-emitting control scan driving circuit includes a second stabilizing capacitor, a first electrode plate of the second stabilizing capacitor is electrically connected to the output terminal, a second electrode plate of the second stabilizing capacitor is electrically connected to the first power line, the second electrode plate of the second stabilizing capacitor includes a first part and a second part, and an organic insulation layer is provided between the first part and the second part.

Abstract: A tandem photovoltaic device includes: a tunnel junction between an upper cell unit and a lower cell unit. The lower cell unit is a crystalline silicon cell. The tunnel junction includes: a carrier transport layer, a crystalline silicon layer, and an intermediate layer located between the carrier transport layer and the crystalline silicon layer. The carrier transport layer is a metal oxide layer. The intermediate layer includes a tunneling layer. The crystalline silicon layer has a doping concentration greater than or equal to 1017 cm?3. The carrier transport layer is in direct contact with a shadow surface of the upper cell unit. If the crystalline silicon layer is a p-type crystalline silicon layer, a first energy level is close to a second energy level. If the crystalline silicon layer is an n-type crystalline silicon layer, a third energy level is close to a fourth energy level.

Abstract: A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel has a display region and a border region that surrounds the display region and includes a peripheral circuit region and a peripheral region; the peripheral circuit region is between the display region and the peripheral region. At least a part of a barrier structure of the display panel is in the peripheral circuit region, and the barrier structure includes an organic barrier layer including an opening passing through the organic barrier layer and an inorganic barrier layer covering the organic barrier layer and filling the opening; an extension direction of the opening is same as that of an edge, close to the opening, of the display panel; the peripheral circuit is in the peripheral circuit region.

Abstract: A tandem photovoltaic device and production method. The tandem photovoltaic device includes: an upper battery cell and a lower battery cell, and a tunnel junction located between the upper battery cell and the battery cell; the lower battery is a crystalline silicon cell; the tunnel junction includes: an upper crystalline silicon layer, a lower crystalline silicon layer and an intermediate layer located between the upper crystalline silicon layer and the lower crystalline silicon layer; the upper crystalline silicon layer, the lower crystalline silicon layer and the intermediate layer are in direct contact, and the doping types of the upper crystalline silicon layer and the lower crystalline silicon layer are opposite; the doping concentration of the upper crystalline silicon layer at the interface with the intermediate layer and the doping concentration of the lower crystalline silicon layer at the interface with the intermediate layer are greater than or equal to 1018 cm?3.