Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a transistor disposed within the first dielectric layer; a second dielectric layer disposed over the first dielectric layer; and a capacitor disposed within the second dielectric layer and electrically connected to the transistor, wherein the capacitor includes a first electrode, a dielectric stack disposed over the first electrode, and a second electrode disposed over the dielectric stack, the dielectric stack includes a ferroelectric layer and an electrostrictive layer. Further, a method of manufacturing a semiconductor structure includes disposing an electrostrictive material over a first electrode layer; disposing a ferroelectric material over the first electrode layer; removing a portion of the ferroelectric material to form the ferroelectric material; and removing a portion of the electrostrictive material to form the electrostrictive layer.

Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a transistor disposed within the first dielectric layer; a second dielectric layer disposed over the first dielectric layer; and a capacitor disposed within the second dielectric layer and electrically connected to the transistor, wherein the capacitor includes a first electrode, a dielectric stack disposed over the first electrode, and a second electrode disposed over the dielectric stack, the dielectric stack includes a ferroelectric layer and an electrostrictive layer. Further, a method of manufacturing a semiconductor structure includes disposing an electrostrictive material over a first electrode layer; disposing a ferroelectric material over the first electrode layer; removing a portion of the ferroelectric material to form the ferroelectric material; and removing a portion of the electrostrictive material to form the electrostrictive layer.

Abstract: A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.

Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: Magnetic field assisted magnetoresistive random access memory (MRAM) structures, integrated circuits including MRAM structures, and methods for fabricating integrated circuits including MRAM structures are provided. An exemplary integrated circuit includes a magnetoresistive random access memory (MRAM) structure and a magnetic field assist structure to generate a selected net magnetic field on the MRAM structure.

Abstract: Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (MTJ) structures are provided. An exemplary method for fabricating an integrated circuit includes forming a magnetic tunnel junction (MTJ) structure and conformally forming a metal oxide encapsulation layer over and around the MTJ structure. The method further includes removing a portion of the metal oxide encapsulation layer over MTJ structure. Also, the method includes forming a conductive via over and in electrical communication with the top surface of the MTJ structure.

Abstract: Magnetic field assisted magnetoresistive random access memory (MRAM) structures, integrated circuits including MRAM structures, and methods for fabricating integrated circuits including MRAM structures are provided. An exemplary integrated circuit includes a magnetoresistive random access memory (MRAM) structure and a magnetic field assist structure to generate a selected net magnetic field on the MRAM structure.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first and second dummy memory cell positioned within a dummy memory bank area. A first dummy top electrode overlies the first and second dummy memory cells, and is in electrical communication with the first and second dummy memory cells. A test circuit is in electrical communication with the first dummy top electrode.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a magnetic tunnel junction. The magnetic tunnel junction includes a fixed layer structure, a free layer structure, and a barrier layer disposed between the fixed layer structure and the free layer structure. The fixed layer structure includes a first magnetic layer and a second magnetic layer that is disposed between the first magnetic layer and the barrier layer. The first magnetic layer is configured to produce a first magnetic moment that substantially correlates to a second magnetic moment of the second magnetic layer as a function of temperature.

Abstract: One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

Abstract: One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a magnetic tunnel junction. The magnetic tunnel junction includes a fixed layer structure, a free layer structure, and a barrier layer disposed between the fixed layer structure and the free layer structure. The fixed layer structure includes a first magnetic layer and a second magnetic layer that is disposed between the first magnetic layer and the barrier layer. The first magnetic layer is configured to produce a first magnetic moment that substantially correlates to a second magnetic moment of the second magnetic layer as a function of temperature.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.