Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, the integrated circuit includes a plurality of magnetic random access memory (MRAM) structures. Each of the MRAM structures includes a bottom electrode. The MRAM structures further include a magnetic tunnel junction stack (MTJ stack) overlying and in electrical communication with the bottom electrode. The MRAM structures also include a top electrode layer overlying and in electrical communication with the MTJ stack. The integrated circuit further includes a spin-on dielectric layer at least partially encapsulating the MRAM structures with the spin-on dielectric layer disposed between adjacent MRAM structures.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell. A bottom electrode and a fixed layer are formed. The fixed layer includes a composite spacer layer disposed on the bottom electrode. The composite spacer layer includes a base layer and an amorphous buffer layer disposed over the base layer. A reference layer is disposed on the composite spacer layer. The amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation. At least one tunneling barrier layer is formed over the fixed layer. A storage layer is formed over the tunneling barrier layer and a top electrode is formed over the storage layer.

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer. The upper ILD layer includes a plurality of ILD levels. A plurality of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. The plurality of MTJ stacks include a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer. The first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface. The plurality of MTJ stacks also include a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer.

Abstract: Memory cells and methods for forming a memory cell are presented. The memory cell includes a storage unit and a selector unit. The storage unit includes a magnetic storage element with first and second storage terminals and a bitline coupled to the second storage terminal. The selector unit includes a first selector and a second selector. The first selector may be a tunneling select transistor or a metal oxide semiconductor select transistor. The second tunneling select transistor is configured to have a second unidirectional current flow between its source and drain terminals. The second selector serves at least as a read selector for read operations of the memory cell and a read current is in the direction of the second unidirectional current flow between the source drain terminals of the second selector.

Abstract: Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfOx. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell. A bottom electrode and a fixed layer are formed. The fixed layer includes a composite spacer layer disposed on the bottom electrode. The composite spacer layer includes a base layer and an amorphous buffer layer disposed over the base layer. A reference layer is disposed on the composite spacer layer. The amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation. At least one tunneling barrier layer is formed over the fixed layer. A storage layer is formed over the tunneling barrier layer and a top electrode is formed over the storage layer.

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer. The upper ILD layer includes a plurality of ILD levels. A plurality of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. The plurality of MTJ stacks include a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer. The first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface. The plurality of MTJ stacks also include a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer.

Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

Abstract: Memory cells and methods for forming a memory cell are presented. The memory cell includes a storage unit and a selector unit. The storage unit includes a magnetic storage element with first and second storage terminals and a bitline coupled to the second storage terminal. The selector unit includes a first selector and a second selector. The first selector may be a tunneling select transistor or a metal oxide semiconductor select transistor. The second tunneling select transistor is configured to have a second unidirectional current flow between its source and drain terminals. The second selector serves at least as a read selector for read operations of the memory cell and a read current is in the direction of the second unidirectional current flow between the source drain terminals of the second selector.