Patents by Inventor Cheng-An Wang

Cheng-An Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153958
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 9, 2024
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240150354
    Abstract: The present application provides tricyclic urea compounds that modulate the activity of the V617F variant of JAK2, which are useful in the treatment of various diseases, including cancer.
    Type: Application
    Filed: August 24, 2023
    Publication date: May 9, 2024
    Inventors: Yanran Ai, Onur Atasoylu, Yu Bai, Joseph Barbosa, David M. Burns, Daniel Levy, Brent Douty, Hao Feng, Leah C. Konkol, Cheng-Tsung Lai, Xun Liu, Song Mei, Jun Pan, Haisheng Wang, Liangxing Wu, Wenqing Yao, Eddy W. Yue
  • Publication number: 20240152649
    Abstract: The disclosure provides a data privacy protection method, a server device, and a client device for federated learning. A public dataset is used to perform model training on a machine learning model by a server device to generate a gradient pool including multiple first gradients. The gradient pool and the machine learning model are received by a client device. The client device uses a local dataset to perform model training on the machine learning model to obtain a second gradient. A local gradient is selected from the first gradients in the gradient pool according to the second gradient using a differential privacy algorithm by the client device. An aggregated machine learning model is generated by performing model aggregation based on the local gradient by the server device.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 9, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Chih Kao, Pang-Chieh Wang, Chia Mu Yu, Kang Cheng Chen
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240153840
    Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Shin-Puu JENG, Po-Yao LIN, Feng-Cheng HSU, Shuo-Mao CHEN, Chin-Hua WANG
  • Publication number: 20240152172
    Abstract: An overshoot-free fast start-up bandgap reference circuit (100), a chip, and an electronic device. The bandgap reference circuit (100) comprises a bias current generating unit (101) and a reference core unit (102), wherein an output end of the bias current generating unit (101) is connected to an input end of the reference core unit (102), the bias current generating unit (101) generates a bias current (IBIAS) unrelated to the voltage of a power supply and having a zero temperature coefficient, the bias current (IBIAS) is an input signal of the reference core unit (102), and the reference core unit (102) generates a pre-charging current on the basis of the input bias current (IBIAS) and implements overshoot-free fast start-up by means of employing pre-charging.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventors: Cheng CHEN, Chunling LI, Yongshou WANG, Chenyang GAO
  • Patent number: 11978678
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 7, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Publication number: 20240146582
    Abstract: An information encoding control method includes: receiving first configuration information, where the first configuration information is used to configure N groups of parameters of N artificial intelligence (AI) encoders or an AI decider, and the AI decider is configured to determine an AI encoder that is in the N AI encoders and to which first information is applicable, and/or is configured to determine that none of the N AI encoders is applicable to encoding the first information; and sending first indication information to a network device, where the first indication information indicates that a first encoder is used for encoding the first information, the first encoder is determined based on the first configuration information and the first information, and the first encoder is an encoder in the N AI encoders, or is a second encoder different from the N AI encoders.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 2, 2024
    Inventors: Sihai WANG, Xueru LI, Cheng QIN, Rui YANG
  • Publication number: 20240142506
    Abstract: A power measurement circuit, a chip and a communication terminal. The power measurement circuit comprises a power measurement unit (100), a reference current generation unit (200), a voltage-current conversion unit (300) and an operation output unit (400), wherein an output end of the power measurement unit (100) is connected to an input end of the voltage-current conversion unit (300), and an output end of the voltage-current conversion unit (300) and an output end of the reference current generation unit (200) are respectively connected to an input end of the operation output unit (400). By means of the circuit, during the process of a power measurement unit (100) converting, into a direct-current voltage, a received radio frequency signal to be measured, sensitivity adjustment is performed, such that the measurement sensitivity can be effectively adjusted.
    Type: Application
    Filed: December 31, 2023
    Publication date: May 2, 2024
    Applicant: SHANGHAI VANCHIP TECHNOLOGIES CO., LTD.
    Inventors: Yongshou WANG, Chunling LI, Cheng CHEN, Chenyang GAO
  • Publication number: 20240140023
    Abstract: The present disclosure provides a method for photo-curing 4D printing of a multi-layer structure with an adjustable shape recovery speed, and a multi-layer structure printed thereby. The multi-layer structure printed by the method for photo-curing 4D printing of the multi-layer structure with the adjustable shape recovery speed includes a plurality of deformation units sequentially connected in series, and each of the plurality of the deformation units includes two slow layers, a fast layer, and a transition layer; and the fast layer is arranged between the two slow layers, and the transition layer is arranged between at least one of the two slow layers and the fast layer. In the present disclosure, a low cross-linking layer is doped with a nanocarbon light-absorbing material to solve the problem that the low cross-linking layer is prone to over-curing when a high cross-linking layer is printed on the low cross-linking layer.
    Type: Application
    Filed: December 16, 2022
    Publication date: May 2, 2024
    Applicant: Jiangsu University
    Inventors: Shu HUANG, Hang ZHANG, Jianzhong ZHOU, Jie SHENG, Jiean WEI, Hongwei YANG, Cheng WANG, Mingyuan SHAN
  • Publication number: 20240142571
    Abstract: A method of radar jamming based on a frequency diverse array jammer is provided. In the method, jamming signals are transmitted through a frequency diverse array, so that the jamming signals transmitted by each array element are different in frequency. On one hand, the power of the jamming signals is enhanced by adopting an array form, which causes serious trouble to the target detection of enemy radar in the frequency domain. The frequency diverse array jammer uses a digital radio frequency memory as a front end basic component, stores and processes the received enemy detection signal, flexibly uses repeater jamming or smart jamming, and finally transmits the jamming signal in a frequency diverse array antenna mode to generate more false targets than conventional jamming, thereby effectively destroying the detection and tracking of the enemy radar on our side moving targets.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 2, 2024
    Inventors: Wenqin WANG, Cheng WANG
  • Publication number: 20240138771
    Abstract: A pulse manifestation determining method is provided. The pulse manifestation method includes following steps. A pulse signal for determination is obtained. A valid range of the pulse signal for determination is determined through identifying a reverse pulse. A pulse manifestation is determined based on the valid range.
    Type: Application
    Filed: July 31, 2023
    Publication date: May 2, 2024
    Applicant: AUO Corporation
    Inventors: Chien Cheng Wang, Jung-Teng Pan, Chin-Tang Chuang
  • Publication number: 20240145470
    Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Lung-Kun CHU, Mao-Lin HUANG, Chung-Wei HSU, Jia-Ni YU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20240143005
    Abstract: A power supply suppression circuit (10), a chip and a communication terminal that only achieve the enhancement of the power supply suppression capability from an AC, without generating additional circuit power consumption. The power supply suppression circuit (10) comprises a sampling unit (105), a compensation unit (106), and an amplification unit (107). The sampling unit (105) is connected to the compensation unit (106), and the compensation unit (106) is connected to the amplification unit (107). The power supply suppression circuit (10) obtains an AC signal from a preset sampling node position of a low dropout regulator, and generates an enhancement signal in phase with the AC signal on a power supply (Vdd) on the basis of the AC signal, such that the input end voltage of the power output stage of the low dropout regulator immediately follows the voltage change of the power supply (Vdd).
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventors: Chunling LI, Yongshou WANG, Cheng CHEN, Sheng LIN
  • Publication number: 20240144098
    Abstract: Aspects of the present disclosure provide an automated labeling system. For example, the automated labeling system can include an automated labeling module (ALM) configured to receive wireless signals and ground truth of learning object and label the wireless signals with the ground truth when receiving the ground truth to generate labeled training data. The automated labeling system can also include a training database coupled to the ALM. The training database can be configured to store the labeled training data.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 2, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chao Peng WANG, Chia-Da LEE, Po-Yu CHEN, Hsiao-Chien CHIU, Yi-Cheng LU
  • Publication number: 20240144160
    Abstract: Systems and methods for reconciling location based on multiple computing device signals. For example, the computing system can obtain location datasets associated with freight carrier services from computing sources. The computing system can determine an expected signal pattern for a location associated with a freight transportation service. The computing system can determine, for each computing source, a confidence score. The confidence score can represent the probability that the respective location dataset is associated with a load being transported for a freight transportation service. The computing system can determine a primary location dataset based on the confidence scores. The computing system can perform actions based on the primary location dataset.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Ajinkya Manoj Deshpande, Mudit Gupta, Siddharth Rane, Martin Alan Tromblee, Jianing Wang, Yu Wang, David Wee, Cheng Wei
  • Publication number: 20240145389
    Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.
    Type: Application
    Filed: July 28, 2023
    Publication date: May 2, 2024
    Inventors: Li-Chiu WENG, Yew Teck TIEO, Ming-Hsuan WANG, Chia-Cheng CHEN, Wei-Yi CHANG, Jen-Hang YANG, Chien-Hsiung HSU
  • Publication number: 20240141476
    Abstract: A method for manufacturing a target material is provided, including the steps of: disposing raw material powder on a substrate and melting the raw material powder by laser to form a target material layer; repeating the preceding process to allow a plurality of target material layers to form an integrated target material column; after cooling the target material column, removing the target material column from the substrate; and performing vacuum heat treatment on the target material column. Since the target material is additively manufactured and subjected to vacuum heat treatment, the target material has a finer and more uniform microstructure, thus improving the product quality.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Applicant: TAIWAN STEEL GROUP AEROSPACE ADDITIVE MANUFACTURING CORPORATION
    Inventors: William HSIEH, Bo-Chen Wu, Chii-Feng Huang, Jun-Cheng Wang
  • Publication number: 20240146036
    Abstract: A bus power distribution micromodule, including a UPS; a channel door containing a bus starting end A; and at least one cabinet containing a bus section A1 or A2, wherein an input end of the bus starting end A is connected to the UPS, an output end thereof is connected to the bus section A1 or A2 by means of a connector, and the bus section A1 or A2 is disposed in the cabinet and connected to a power distribution apparatus of the cabinet. In the bus power distribution micromodule, a plug-and-play property, easy expansion and IT load flexible matching of the cabinet are realized; the bus starting end is integrated in the channel door of the micromodule, thereby facilitating convenient maintenance and operation; the beneficial effect of having a small, occupied area is achieved; and, moreover, the bus power distribution micromodule has the advantage of rapid delivery.
    Type: Application
    Filed: May 27, 2021
    Publication date: May 2, 2024
    Applicant: VERTIV TECH (XI’AN ) CO., LTD.
    Inventors: Cheng GAO, Xiaobo FENG, Xing LI, Xin LIU, Tengjiang WANG
  • Publication number: 20240143042
    Abstract: A computer case assembly is adapted for computer component units of a computer system to be mounted to. The computer component units include a motherboard and a power supply unit. The computer case assembly includes a main case module and a power case module. The main case module includes a main frame that is cuboid-shaped and that is adapted for the motherboard to be mounted to. The power case module includes a power case frame that is cuboid-shaped, that is adapted for the power supply unit to be mounted to, and that is detachably mounted to the main frame.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 2, 2024
    Inventors: Ling-Cheng TSAO, Chao-Hung WANG