Patents by Inventor Cheng-Hsien Lee
Cheng-Hsien Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10820410Abstract: A high speed circuit and a method for fabricating the same is disclosed. The high speed circuit has a printed circuit board. A pair of first and second differential traces are formed on a first surface of the printed circuit board. The differential traces carry an electrical signal. A partial loop extends through the printed circuit board. The partial loop includes first and second end slots under the first and second differential traces. The partial loop includes a pair of side slots substantially parallel to the differential traces. An anchor member connects the printed circuit board to an island formed by the first and second end slots and side slots. The anchor member forms a gap in one of the end slots or side slots. The length of the side slots and the length of the gap is selected to reduce a target common mode frequency from the electrical signal.Type: GrantFiled: March 4, 2019Date of Patent: October 27, 2020Assignee: QUANTA COMPUTER INC.Inventor: Cheng-Hsien Lee
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Patent number: 10784607Abstract: A connector assembly is disclosed to reduce discontinuity impedance between golden finger connectors and components on a circuit board. The assembly includes a circuit board including a connector edge. A plurality of connectors is formed on the connector edge on a first surface of the circuit board. A ground plane is formed on part of the circuit board on a second opposite surface of the first surface. The ground plane leaves the second opposite surface under the connector edge exposed. A ground loop is formed on the second opposite surface under at least two of the plurality of connectors.Type: GrantFiled: May 21, 2019Date of Patent: September 22, 2020Assignee: QUANTA COMPUTER INC.Inventor: Cheng-Hsien Lee
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Publication number: 20200288566Abstract: A high speed circuit and a method for fabricating the same is disclosed. The high speed circuit has a printed circuit board. A pair of first and second differential traces are formed on a first surface of the printed circuit board. The differential traces carry an electrical signal. A partial loop extends through the printed circuit board. The partial loop includes first and second end slots under the first and second differential traces. The partial loop includes a pair of side slots substantially parallel to the differential traces. An anchor member connects the printed circuit board to an island formed by the first and second end slots and side slots. The anchor member forms a gap in one of the end slots or side slots. The length of the side slots and the length of the gap is selected to reduce a target common mode frequency from the electrical signal.Type: ApplicationFiled: March 4, 2019Publication date: September 10, 2020Inventor: Cheng-Hsien LEE
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Publication number: 20200275566Abstract: The present disclosure describes an expansion card interface for a printed circuit board. The expansion card interface includes a substrate having an edge. The expansion card interface further includes a plurality of signal pins configured to communicate one or more signals to and from the printed circuit board. The expansion card interface further includes a plurality of ground pins adjacent to the plurality of signal pins configured to provide a ground. At least one signal pin of the plurality of signal pins extends closer to the edge of the substrate than at least one ground pin of the plurality of ground pins.Type: ApplicationFiled: December 5, 2019Publication date: August 27, 2020Inventor: Cheng-Hsien Lee
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Publication number: 20200212610Abstract: A connector assembly is disclosed to reduce discontinuity impedance between golden finger connectors and components on a circuit board. The assembly includes a circuit board including a connector edge. A plurality of connectors is formed on the connector edge on a first surface of the circuit board. A ground plane is formed on part of the circuit board on a second opposite surface of the first surface. The ground plane leaves the second opposite surface under the connector edge exposed. A ground loop is formed on the second opposite surface under at least two of the plurality of connectors.Type: ApplicationFiled: May 21, 2019Publication date: July 2, 2020Inventor: Cheng-Hsien LEE
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Patent number: 10667384Abstract: A differential trace structure reducing the magnitude of low frequency attenuation is disclosed. The trace structure is formed on a printed circuit board. A pair of differential traces connects a signal receiver and a signal transmitter. A passive equalizer has a first shunt coupled to one of the pair of differential traces; and a second shunt coupled to the other one of the pair of differential traces. The passive equalizer has an inductor and a resistor coupled in series to the shunts. For low frequency signals, the passive equalizer behaves as a shunt resistance to the pair of differential traces.Type: GrantFiled: July 17, 2018Date of Patent: May 26, 2020Assignee: QUANTA COMPUTER INC.Inventor: Cheng-Hsien Lee
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Publication number: 20200029434Abstract: This disclosure relates to a Golden Finger card design where the PCB edge has a first thickness, but the main body of the PCB is of increased thickness to accommodate application complexity. The increased thickness in the body portion provides greater dielectric material between traces, thereby reducing loss. By maintaining the edge of the PCB fingers at a first thickness, the use of existing connectors, such as standard PCIe connectors, is maintained. Golden Finger cards of this disclosure are used as a video and graphics card, network adapter card, audio adapter card, and television or other specialty adapter card.Type: ApplicationFiled: July 23, 2018Publication date: January 23, 2020Inventors: Yu-Tsung HSU, Cheng-Hsien LEE
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Publication number: 20200029422Abstract: A differential trace structure reducing the magnitude of low frequency attenuation is disclosed. The trace structure is formed on a printed circuit board. A pair of differential traces connects a signal receiver and a signal transmitter. A passive equalizer has a first shunt coupled to one of the pair of differential traces; and a second shunt coupled to the other one of the pair of differential traces. The passive equalizer has an inductor and a resistor coupled in series to the shunts. For low frequency signals, the passive equalizer behaves as a shunt resistance to the pair of differential traces.Type: ApplicationFiled: July 17, 2018Publication date: January 23, 2020Inventor: Cheng-Hsien LEE
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Patent number: 10499490Abstract: A high speed differential trace structure reducing common mode radiation is disclosed. The differential trace structure includes a first trace and a parallel second trace. A printed circuit board layer has a top surface and an opposite bottom surface. The traces are formed on the top surface. The structure includes a ground plane layer having a top layer in contact with the opposite bottom surface of the circuit board. A first void section is formed in the top layer of the ground plane layer to one side of the first trace. A second void section is formed in the top layer of the ground plane layer to one side of the second trace. The length of the second void section is determined based on a target radiation frequency. A third void section is formed in the ground plane layer that joins the first void section and the second void section.Type: GrantFiled: February 7, 2018Date of Patent: December 3, 2019Assignee: QUANTA COMPUTER INC.Inventor: Cheng-Hsien Lee
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Publication number: 20190166685Abstract: A high speed differential trace structure reducing common mode radiation is disclosed. The differential trace structure includes a first trace and a parallel second trace. A printed circuit board layer has a top surface and an opposite bottom surface. The traces are formed on the top surface. The structure includes a ground plane layer having a top layer in contact with the opposite bottom surface of the circuit board. A first void section is formed in the top layer of the ground plane layer to one side of the first trace. A second void section is formed in the top layer of the ground plane layer to one side of the second trace. The length of the second void section is determined based on a target radiation frequency. A third void section is formed in the ground plane layer that joins the first void section and the second void section.Type: ApplicationFiled: February 7, 2018Publication date: May 30, 2019Inventor: Cheng-Hsien LEE
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Publication number: 20150012904Abstract: A computer-based method for setting electrical specification of signal transmission lines of a printed circuit board (PCB) layout is provided. Data recorded in an electrical specification file is imported. The electrical specification file records a number of chips, pins of each chip, and electrical specification corresponding to each chip. The PCB layout is searched to find the chips and the pins recorded in the electrical specification file. The electrical specification of signal transmission lines connected to the found pins is set according to the electrical specification corresponding to each chip.Type: ApplicationFiled: November 22, 2013Publication date: January 8, 2015Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHENG-HSIEN LEE, SHIN-TING YEN
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Patent number: 8913654Abstract: In a data processing device and a method for analyzing stability of the data processing device, one or more sets of equalization parameters and a predetermined bit error ratio (BER) are received. Times and voltages of data points that represent a waveform of an electronic signal generated by the data processing device are read, and an output type of the electronic signal is selected to obtain a time interval of outputs of the electronic signal. Optimal equalization parameters are selected from the one or more sets of equalization parameters to compute a sample interval. Interfering voltages of the electronic signal are computed to select a frequency which is equal to the predetermined BER, and the interfering voltages corresponding to the selected frequency are obtained. An eye pattern is established using the interfering voltages corresponding to the selected frequency, and a determination is made according to the eye pattern.Type: GrantFiled: January 15, 2013Date of Patent: December 16, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Cheng-Hsien Lee, Shou-Kuo Hsu
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Patent number: 8838272Abstract: A robotic arm control system is provided. In, the robotic arm control system, any three points A, B, and C of an object to be determined are picked, thereby creating an original coordinate system. A robotic arm is directed to rotate around the x-axis of the original coordinate system to reach the points B and C. During the rotation of the robotic arm, the three points A, B, and C are recorded by a visual process. A non-linear mapping relation of the original coordinate system and the operation coordinate system is calculated according to length ratios, an angular ratio, and a differential ratio of the difference of the length ratios to the angle between the line A-B and the line A-C, thereby controlling the movement of the robotic arm according to the non-linear mapping relation. The disclosure further provides a robotic arm control method.Type: GrantFiled: December 22, 2011Date of Patent: September 16, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Chun-Neng Liao, Shen-Chun Li, Wen-Laing Tseng, Cheng-Hsien Lee, Shou-Kuo Hsu
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Patent number: 8798968Abstract: A computing device and a method for scattering parameter equivalent circuit reads a scattering parameter file from a storage device. A non-common-pole rational function of the scattering parameters in the scattering parameter file is created by applying a vector fitting algorithm to the scattering parameters. Passivity of the non-common-pole rational function is enforced if the non-common-pole rational function does not satisfy a determined passivity requirement.Type: GrantFiled: October 25, 2011Date of Patent: August 5, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Wen-Laing Tseng, Yu-Chang Pai, Cheng-Hsien Lee, Shen-Chun Li, Shou-Kuo Hsu
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Patent number: 8766740Abstract: An equalizer for compensating transmission losses of electronic communication signals includes a circuit board and a compensation module. The compensation module includes a pair of input pins, a pair of output pins, and at least two resistors. When a signal transmitted by the circuit board is received by the input pins, a first portion of the signal is directly output from the output pins, a second portion of the signal is reflected by the first resistor and transmitted back to the output pins to output, and a third portion of the signal is reflected by the second resistor and transmitted back to the output pins to output, such that output of the equalizer applies two stages of compensation.Type: GrantFiled: November 27, 2012Date of Patent: July 1, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Po-Chuan Hsieh, Ying-Tso Lai, Cheng-Hsien Lee, En-Shuo Chang
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Patent number: 8626482Abstract: A simulation system for producing equivalent circuits reads data corresponding to a tabular W element format in a storage device, and adds data of the tabular W element format file using interpolation algorithm. A frequency-dependent transmission matrix is transformed into an N-port network matrix describing electrical properties of a multi-input and multi-output network. An N-port network matrix is transformed into a S-parameter matrix. A range of frequency of a s-parameter is determined and numbers of pole-residue, times for recursion and durable maximum system errors in the equivalent circuit is also determined. A vector fitting algorithm is performed and a rational function matrix composed with s-parameters is produced, to produce a general SPICE equivalent circuit based on the generated rational function matrix.Type: GrantFiled: December 2, 2010Date of Patent: January 7, 2014Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Wen-Laing Tseng, Cheng-Hsien Lee, Shen-Chun Li, Yu-Chang Pai, Shou-Kuo Hsu
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Patent number: 8571846Abstract: In an electronic device and a method of generating composite electrical signals, a plurality of post-processing software is installed. An output file, which comprises times and voltages of data points that represent an electrical signal, of an electronic circuit simulation software is loaded, and is read using the installed post-processing software. A time interval of outputs of the electrical signal is obtained by selecting an output type of the electrical signal. The worst bit combination of outputs of the electrical signal is analyzed according to the times, the voltage, and the time interval, and a composite electrical signal is generated according to the worst bit combination.Type: GrantFiled: December 24, 2010Date of Patent: October 29, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Cheng-Hsien Lee, Shou-Kuo Hsu
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Publication number: 20130272363Abstract: An equalizer for compensating transmission losses of electronic communication signals includes a circuit board and a compensation module. The compensation module includes a pair of input pins, a pair of output pins, and at least two resistors. When a signal transmitted by the circuit board is received by the input pins, a first portion of the signal is directly output from the output pins, a second portion of the signal is reflected by the first resistor and transmitted back to the output pins to output, and a third portion of the signal is reflected by the second resistor and transmitted back to the output pins to output, such that output of the equalizer applies two stages of compensation.Type: ApplicationFiled: November 27, 2012Publication date: October 17, 2013Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: PO-CHUAN HSIEH, YING-TSO LAI, CHENG-HSIEN LEE, EN-SHUO CHANG
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Patent number: 8547819Abstract: A computing device and a method reads a circuit board layout file from a storage device, and selects a first signal transmission line from circuit board layout file as a target line. The computing device and method computes a distance between the target line and the aggressor line corresponding to each unit sample length. If the distance is more than or equal to a height of a sample region, the computing device and method defines the height of the sample region as a crosstalk space between the target line and the aggressor line corresponding to a unit sample length. Otherwise, if the distance is less than the height of the sample region, the computing device and method defines the distance as the crosstalk space between the target line and the aggressor line corresponding to the unit sample length.Type: GrantFiled: December 7, 2010Date of Patent: October 1, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Tso Lai, Shi-Piao Luo, Cheng-Hsien Lee
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Publication number: 20130238682Abstract: A signal-equalizing system for multi-rate signals and a signal-equalizing method for the system are provided. The system stores a number of compensation methods of equalization. The method includes the steps: acquiring all transmission rates of a multi-rate signal, loading output documents of a signal simulation software, wherein the output documents comprise channel loss values of all transmission rates of the multi-rate signal and selecting a compensation method based on channel loss in the course of the multi-rate signal transmitted and differences among all transmission rates of the multi-rate signal from the plurality of compensation methods of equalization.Type: ApplicationFiled: June 20, 2012Publication date: September 12, 2013Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHENG-HSIEN LEE, SHOU-KUO HSU