Abstract: A pseudo-analog memory computing circuit includes at least one input circuit, at least one output circuit and at least one pseudo-analog memory computing unit. Each pseudo-analog memory computing unit is coupled between one of the at least one input circuit and one of the at least one output circuit and has at least one weight mode. Each pseudo-analog memory computing unit generates at least first computing result for a coupled output circuit according to a weight of a selected weight mode and at least one input signals of a coupled input circuit.

Abstract: A pseudo-analog memory computing circuit includes at least one input circuit, at least one output circuit and at least one pseudo-analog memory computing unit. Each pseudo-analog memory computing unit is coupled between one of the at least one input circuit and one of the at least one output circuit and has at least one weight mode. Each pseudo-analog memory computing unit generates at least first computing result for a coupled output circuit according to a weight of a selected weight mode and at least one input signals of a coupled input circuit.

Abstract: Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.

Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

Abstract: Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.

Abstract: By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.

Abstract: A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.

Abstract: A memory device including a substrate, a plurality of conductive layers, a composite dielectric layer and a plurality of gates are provided. Wherein, the conductive layers are disposed on the substrate. The composite dielectric layer is disposed on the substrate and covers the conductive layers. The composite dielectric layer includes a charge trapping layer. The gates are disposed on the composite dielectric layer and across the conductive layers. Wherein, the conductive layers can be used as local bit lines to reduce the resistance values and improve the performance of the memory device.

Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

Abstract: A system for operating a memory device includes a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic reference provides the associated memory cells with a dynamic reference value for determining a status of at least one of the associated memory cells. The dynamic reference value is capable of reflecting a variation in a threshold value of at least one of the associated memory cells.

Abstract: A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.

Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

Abstract: The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first International Mobile Equipment Identity (IMEI) code; and a storage device comprising a first storage region for storing data, a second storage region for storing a second IMEI code, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first IMEI code.

Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

Abstract: A read operation method is provided for a flash memory array having a plurality of memory cells, wordlines, even bitlines, odd bitlines and a plurality of bitline transistors. The method includes pre-charging the plurality of even bitlines to about Vcc/n and pre-charging the plurality of odd bitlines to ground. The current flowing to/from a first bit location in each of the memory cells is selectively sensed. A logical state is determined from the sensed current for the first bit location in each of the memory cells. The method also includes pre-charging the plurality of odd bitlines to about Vcc/n and pre-charging the plurality of even bitlines to ground. The current flowing to/from a second bit location in each of the memory cells is selectively sensed. A logical state is determined from the sensed current for the second bit location in each of the memory cells.

Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

Abstract: The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first Subscriber Identity Module (SIM) specification corresponding to a SIM card; and a storage device comprising a first storage region for storing data, a second storage region for storing a second SIM specification, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first SIM specification.

Abstract: The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first International Mobile Equipment Identity (IMEI) code; and a storage device comprising a first storage region for storing data, a second storage region for storing a second IMEI code, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first IMEI code.

Abstract: A data accessing system includes a host computer and a storage device. The host computer has a first media access control (MAC) address, and the storage device includes a first storage region, a second storage region, and a controller. The first storage region is utilized for storing data. The second storage region stores a second media access control address. The controller couples to the first storage region and the second storage region for executing a security checking function to determine if the host computer is qualified to access the first storage region according to the first media access control address.

Abstract: A system for operating a memory device comprises a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic reference provides the associated memory cells with a dynamic reference value for determining a status of at least one of the associated memory cells. The dynamic reference value is capable of reflecting a variation in a threshold value of at least one of the associated memory cells.