Patents by Inventor Cheng-Wei Lin

Cheng-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097011
    Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
  • Publication number: 20240096805
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20240099086
    Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 21, 2024
    Inventors: Cheng-Ho Yu, Chin-Wei Lin, Shyuan Yang, Ting-Kuo Chang, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shih-Chang Chang, Yu Cheng Chen, John Z. Zhong
  • Patent number: 11935841
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: March 19, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
  • Publication number: 20240078979
    Abstract: An electronic device including a display device is provided. The display device includes a sharing area, a junction area, and a privacy area. The junction area is positioned between the sharing area and the privacy area. The display device includes a privacy panel. A transmittance of the privacy panel corresponding to the sharing area is greater than a transmittance of the privacy panel corresponding to the junction area, and the transmittance of the privacy panel corresponding to the junction area is greater than a transmittance of the privacy panel corresponding to the privacy area.
    Type: Application
    Filed: August 8, 2023
    Publication date: March 7, 2024
    Applicants: Innolux Corporation, CARUX TECHNOLOGY PTE. LTD.
    Inventors: Li-Wei Sung, Chia-Hsien Lin, Cheng-Wu Lin, Yu-Ming Wu
  • Publication number: 20240076422
    Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
  • Publication number: 20240068119
    Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.
    Type: Application
    Filed: March 2, 2023
    Publication date: February 29, 2024
    Applicant: Acer Incorporated
    Inventors: Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
  • Publication number: 20240071947
    Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
  • Publication number: 20240069618
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
  • Publication number: 20230409637
    Abstract: A method of building a knowledge graph, performed by a processing device, includes: classifying news articles to a main event associated with sub events, using the main event as a first node of the knowledge graph, using the sub events as second nodes of the knowledge graph respectively, connecting the second nodes to the first node, extracting event summaries from the news articles respectively according to a template, using the event summaries as third nodes of the knowledge graph respectively, and connecting each of the third nodes to one of the second nodes according to association between the event summaries and the sub events, extracting commenter identities from the event summaries, and using the commenter identities as fourth nodes of the knowledge graph, and connecting each of the fourth nodes to one of the third nodes.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 21, 2023
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Wen-Hsiang LU, Cheng-Wei LIN, Bo Yang HUANG, Chia-Ming TUNG
  • Patent number: 11783471
    Abstract: A method and device for determining whether an object includes a defect are provided. The method includes the following steps. A tested image of a tested object is obtained. Selected good product sample data corresponding to the tested object is obtained. A dissimilarity value between the tested image and the selected good product sample data is calculated by using a dissimilarity model, and whether the tested object is a good product or a defective product is determined according to the dissimilarity value.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: October 10, 2023
    Assignee: Wistron Corporation
    Inventor: Cheng-Wei Lin
  • Publication number: 20230186469
    Abstract: The present invention relates to a method for improving the diagnostic accuracy of an artificial intelligence (AI) to diagnose osteoarthritis (OA). The method involves all or some steps of: generating a plurality of feature values from at least one input skeletal image, generating a quantitative Kellgren-Lawrence (KL) grade based on the plurality of feature values, and generating an explanation plot showing the contributions of each feature. The present invention also relates to a method of constructing a non-transitory computer-readable medium to perform the above tasks.
    Type: Application
    Filed: December 12, 2022
    Publication date: June 15, 2023
    Inventors: CHANG-CHOU YEN, WIN-HOW LEE, QING-ZONG TSENG, CHENG-WEI LIN
  • Patent number: 11638369
    Abstract: A heat dissipating mechanism is for heat dissipation of a display module and a heat generating module of a display apparatus and includes a frame structure, a first airflow generating device, and a conductive cover structure having first, second, and third covers. The first cover is connected to the frame structure for containing the display module. The second cover has an air inlet and an air outlet and is connected to the first cover to form a channel. The third cover is connected to the second cover for containing the heat generating module. The first airflow generating device is disposed in the air inlet to guide air into the channel and out of the air outlet, so as to form an airflow for heat dissipation of the display module and the heat generating module.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: April 25, 2023
    Assignee: Wistron Corporation
    Inventors: Chun-Yi Lin, Chien-Tsung Lee, Cheng-Wei Lin, Jen-Kung Li
  • Publication number: 20230110837
    Abstract: The present invention relates to a method to improve quality control (QC) accuracy. The method comprises at least one input quality control (IQC) check and at least one output quality control (OQC) check for the image to be analyzed. The integrated IQC and OQC results may be mapped onto a pre-defined multi-dimensional space to evaluate the overall QC result.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 13, 2023
    Inventors: QING-ZONG TSENG, CHENG-WEI LIN, PO-YU CHEN
  • Publication number: 20220354030
    Abstract: A heat dissipating mechanism is for heat dissipation of a display module and a heat generating module of a display apparatus and includes a frame structure, a first airflow generating device, and a conductive cover structure having first, second, and third covers. The first cover is connected to the frame structure for containing the display module. The second cover has an air inlet and an air outlet and is connected to the first cover to form a channel. The third cover is connected to the second cover for containing the heat generating module. The first airflow generating device is disposed in the air inlet to guide air into the channel and out of the air outlet, so as to form an airflow for heat dissipation of the display module and the heat generating module.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 3, 2022
    Applicant: Wistron Corporation
    Inventors: Chun-Yi Lin, Chien-Tsung Lee, Cheng-Wei Lin, Jen-Kung Li
  • Publication number: 20220250934
    Abstract: Disclosed herein, in certain embodiments, are compounds, methods, tools, and abrasive materials comprising mixed transition metal dodecaborides.
    Type: Application
    Filed: September 17, 2021
    Publication date: August 11, 2022
    Applicant: The Regents of the University of California
    Inventors: Richard Barry Kaner, Georgiy Akopov, Michael Tyrone Yeung, Christopher Lawrence Turner, Zachary C. Sobell, Cheng-Wei Lin
  • Patent number: 11398797
    Abstract: A crystal oscillator and a method for fabricating the same is provided. In the method, a crystal package is provided. The crystal package includes a crystal blank and at least one laser-penetrating area. The laser-penetrating area is exposed outside. The crystal package is provided with at least one airtight space therein. At least one getter is formed in the airtight space. The location of the laser-penetrating area corresponds to that of the getter. A laser beam penetrates through the laser-penetrating area to activate the getter, thereby increasing the degree of vacuum of the airtight space.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: July 26, 2022
    Assignee: TXC CORPORATION
    Inventors: Wun-Kai Wang, Cheng-Wei Lin, Chih Hung Chiu, Chih Hsun Chu
  • Publication number: 20220101720
    Abstract: A traffic status display system for displaying a traffic status display picture is disclosed. The traffic status display picture includes a map information including a plurality of intersection traffic statuses, wherein each intersection traffic status of the plurality of intersection traffic statuses includes a traffic light status display picture configured to display a traffic light status of each sub-intersection of an intersection; and a traffic turning vector display picture, configured to display a flow-out table and a flow-in table of the intersection according to a vehicle traffic data.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 31, 2022
    Inventors: Chia-Hsien Huang, Cheng-Wei Lin
  • Patent number: 11249517
    Abstract: An electronic apparatus and its screen control method adapted to an electronic apparatus are provided. The electronic apparatus includes a first display screen, a second display screen, and a body. The first display screen is pivotally connected to the body along a first rotation axis, and the second display screen is disposed on an upper surface of the body. The method includes following steps. A sight of a user is detected by a sight sensor. In response to the sight projected on the second display screen at a default position, a screen rotation degree is determined according to a direction of the sight. According to the screen rotation degree, the second display screen is controlled to rotate from the default position along the second rotation axis to a display position, so that a view angle at which the user watches the second display screen satisfies a predetermined condition.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: February 15, 2022
    Assignee: Acer Incorporated
    Inventors: Cheng-Wei Lin, Wei-Kuo Shih, Chao-Kuang Yang
  • Patent number: 11183513
    Abstract: A semiconductor device includes a substrate, a stacked structure disposed on the substrate, and dummy memory string structures. The stacked structure includes alternately stacked insulating layers and conductive layers. The dummy memory string structures disposed in a staircase region of the semiconductor device penetrate the stacked structure along a first direction. The staircase region includes a body portion including a first region and a second region adjacent to the first region. In the first region, an amount of conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, an amount of conductive layers corresponding to the dummy memory string structures is greater than 10. An area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second area under an identical unit area in a top view.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 23, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jr-Meng Wang, Cheng-Wei Lin, Kuang-Wen Liu