Abstract: A three-dimensional semiconductor device is provided, includes a substrate having an array area and a staircase area; a stack structure having multi-layers formed on the substrate, and the multi-layers comprising conductive layers alternating with insulating layers on the substrate, the stack structure comprising cell-stacks formed on the substrate and disposed in the array area; a conductive channel formed on the substrate and disposed by extending vertically to the multi-layers in the array area; a conductive plug formed on the conductive channel; and a plug contact formed on the conductive plug. The conductive plug includes a polysilicon portion formed on and electrically connected to the conductive channel, and a metal-containing portion formed on the polysilicon portion, wherein the plug contact is electrically connected to the metal-containing portion.

Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Abstract: Disclosed herein, in certain embodiments, are compounds, methods, tools, and abrasive materials comprising mixed transition metal dodecaborides.

Abstract: A flow guiding device includes a flow-guiding member and a blade. The flow-guiding member includes a flow-guiding portion, a neck portion and a first coupling portion. The flow-guiding portion is connected to a first end of the neck portion. The first coupling portion is located at a second end of the neck portion. The flow-guiding portion, the neck portion and the first coupling portion are connected in series in a radial direction. The blade includes a second coupling portion at a free end of the blade. The second coupling portion is coupled with the first coupling portion. The flow-guiding portion has a cross-sectional area smaller than or equal to a cross-sectional area of the blade. A cross-sectional area of the neck portion viewed from the radial direction at the first end is smaller than a cross-sectional area of the neck portion viewed from the radial direction at the second end.

Abstract: A ceiling fan includes a motor and a heat-dissipating device. The heat-dissipating device includes a plurality of blades and a plurality of end plates. The motor includes a shaft and a hub. The hub includes a plurality of vents and a plurality of first coupling portions. Each blade is coupled with at least one first coupling portion and includes a first end and a second end. Each blade forms a second coupling portion at the first end thereof. The second coupling portion is coupled with the at least one first coupling portion. Each blade includes a first air channel extending in a radial direction. The first air channel includes first and second ends. The first end of the first air channel is relatively adjacent to the vents than the second end is. Each end plate includes at least one third coupling portion coupled with the second end of the blade.

Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Abstract: A retractable virtual reality device includes a rear cover, a front cover, a first restraining component, a second restraining component, and a display module. The front cover is movably combined with the rear cover. The first restraining component is fixed on the front cover. The second restraining component is movably disposed on the rear cover and for restraining the first restraining component. The display module includes a sleeve, a lens, and a display. The sleeve is fixed on the rear cover. The lens is disposed on a side of the sleeve. The display is disposed on the front cover and movably combined with the other side of the sleeve. By cooperation of the first restraining component and the second restraining component, the display and the front cover are movable relative to the lens and the rear cover, which reduces an overall size of the virtual reality device for easy carry.

Abstract: A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.

Abstract: A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.

Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Abstract: Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.

Abstract: An air-guiding casing of a ventilation fan includes a main body and an air-guiding tube. The main body forms a compartment and includes an inlet and an outlet. The inlet and the outlet are in communication with the compartment. A first engaging portion is arranged on a part of an edge of the outlet and on one side of the main body. The air-guiding tube has an engaging end and an outlet end opposite to the engaging end. A second engaging portion is arranged on the engaging end. The first and second engaging portions are engaged with each other.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract: A method of manufacturing nitrone compounds is provided. The method includes: providing a nitro compound; and performing a photoreaction of the nitro compound, a catalyst and an additive under visible light to obtain the nitrone compound.

Abstract: A carrier includes a frame defining a first space configured to accommodate a first type of hard disk drive, and an adjusting mechanism slidably coupled to the frame. The adjusting mechanism is transitionable between: (i) a first configuration in which the adjusting mechanism is located outside the first space defined by the frame, and (ii) a second configuration in which the adjusting mechanism is located inside the first space, the adjusting mechanism and the frame cooperatively define a second space configured to accommodate a second type of hard disk drive different from the first type of hard disk drive.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract: A carrier includes a frame defining a first space configured to accommodate a first type of hard disk drive, and an adjusting mechanism slidably coupled to the frame. The adjusting mechanism is transitionable between: (i) a first configuration in which the adjusting mechanism is located outside the first space defined by the frame, and (ii) a second configuration in which the adjusting mechanism is located inside the first space, the adjusting mechanism and the frame cooperatively define a second space configured to accommodate a second type of hard disk drive different from the first type of hard disk drive.

Abstract: A method of manufacturing nitrone compounds is provided. The method includes: providing a nitro compound; and performing a photoreaction of the nitro compound, a catalyst and an additive under visible light to obtain the nitrone compound.

Abstract: Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.