Patents by Inventor Cheng-Ying Huang
Cheng-Ying Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916118Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.Type: GrantFiled: April 4, 2023Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
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Publication number: 20240047559Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Inventors: Willy RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Patrick MORROW, Anh PHAN, Cheng-Ying HUANG, Ehren MANNEBACH
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Patent number: 11894372Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.Type: GrantFiled: January 11, 2023Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron Lilak, Patrick Morrow, Anh Phan, Ehren Mannebach, Jack T. Kavalieros
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Patent number: 11887988Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.Type: GrantFiled: August 1, 2019Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Ashish Agrawal, Jack Kavalieros, Anand Murthy, Gilbert Dewey, Matthew Metz, Willy Rachmady, Cheng-Ying Huang, Cory Bomberger
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Publication number: 20240006499Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Cheng-Ying Huang, Kai Loon Cheong, Pooja Nath, Susmita Ghose, Rambert Nahm, Natalie Briggs, Charles C. Kuo, Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Jack T. Kavalieros, Thoe Michaelos, David Kohen
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Patent number: 11862715Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.Type: GrantFiled: May 16, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Cheng-Ying Huang, Jack Kavalieros, Ian Young, Matthew Metz, Willy Rachmady, Uygar Avci, Ashish Agrawal, Benjamin Chu-Kung
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Patent number: 11862636Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.Type: GrantFiled: April 27, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Nicole Thomas, Ehren Mannebach, Cheng-Ying Huang, Marko Radosavljevic
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Publication number: 20230420460Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Cheng-Ying Huang, Patrick Morrow, Quan Shi, Rohit Galatage, Nicole K. Thomas, Munzarin F. Qayyum, Jami A. Wiedemer, Gilbert Dewey, Mauro J. Kobrinsky, Marko Radosavljevic, Jack T. Kavalieros
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Publication number: 20230420562Abstract: Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Cheng-Ying Huang, Munzarin F. Qayyum, Nicole K. Thomas, Rohit Galatage, Patrick Morrow, Jami A. Wiedemer, Marko Radosavljevic, Jack T. Kavalieros
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Publication number: 20230420528Abstract: An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Nitesh Kumar, Willy Rachmady, Cheng-Ying Huang, Rohit Galatage, Patrick Morrow, Marko Radosavljevic, Jami A. Wiedemer, Subrina Rafique, Mauro J. Kobrinsky
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Publication number: 20230402513Abstract: An integrated circuit structure includes a device including a source region, a drain region, a body laterally between the source and drain regions, and a source contact coupled to the source region. In an example, the source region includes a first region, and a second region compositionally different from and above the first region. The source contact extends through the second region and extends within the first region. In an example where the device is a p-channel metal-oxide-semiconductor (PMOS) device, a concentration of germanium within the second region is different (e.g., higher) than a concentration of germanium within the first region. In another example where the device is a n-channel metal-oxide-semiconductor (NMOS) device, a doping concentration level of a dopant (e.g., an n-type dopant) within the second region is different (e.g., higher) from a doping concentration level of the dopant within the first region.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Rohit Galatage, Willy Rachmady, Subrina Rafique, Nitesh Kumar, Cheng-Ying Huang, Jami A. Wiedemer, Nicloe K. Thomas, Munzarin F. Qayyum, Patrick Morrow, Marko Radosavljevic, Mauro J. Kobrinsky
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Publication number: 20230402507Abstract: An integrated circuit structure includes a second device stacked vertically above a first device. The first device includes (i) a first source or drain region, (ii) a first source or drain contact coupled to the first source or drain region, and (iii) a first layer comprising a first metal and first one or more semiconductor materials between at least a section of the first source or drain region and the first source or drain contact. The second device includes (i) a second source or drain region, (ii) a second source or drain contact coupled to the second source or drain region, and (iii) a second layer comprising a second metal and second one or more semiconductor materials between at least a section of the second source or drain region and the second source or drain contact. In an example, the first metal and the second metal are different.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Rohit Galatage, Willy Rachmady, Cheng-Ying Huang, Jami A. Wiedemer, Munzarin F. Qayyum, Nicole K. Thomas, Patrick Morrow, Marko Radosavljevic, Mauro J. Kobrinsky
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Publication number: 20230395678Abstract: A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Munzarin F. Qayyum, Nicole K. Thomas, Jami A. Wiedemer, Jack T. Kavalieros, Marko Radosavljevic, Willy Rachmady, Cheng-Ying Huang, Rohit Galatage, Nitesh Kumar, Kai Loon Cheong, Venkata Vasiraju
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Publication number: 20230395717Abstract: An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Willy Rachmady, Nitesh Kumar, Jami A. Wiedemer, Cheng-Ying Huang, Marko Radosavljevic, Mauro J. Kobrinsky, Patrick Morrow, Rohit Galatage, David N. Goldstein, Christopher J. Jezewski
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Publication number: 20230395697Abstract: A semiconductor structure includes a second device stacked over a first device. In an example, the first device includes (i) a first source region, (ii) a first drain region, (iii) a body including a semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. The body can be, for instance, a nanoribbon, nanosheet, or nanowire. In an example, the second device comprises (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the second device lacks a continuous body extending laterally from the second source region to the second drain region.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Cheng-Ying Huang, Willy Rachmady, Rohit Galatage, Jami A. Wiedemer, David Bennett, Dincer Unluer, Venkata Aditya Addepalli
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Publication number: 20230395718Abstract: An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device. The first device includes (i) a first source and first drain region, (ii) a first body laterally between the first source and drain regions, (iii) a first source contact including a first conductive material, and (iv) a first drain contact including the first conductive material. The second device includes (i) a second source and second drain region, (ii) a second body laterally between the second source and drain regions, (iii) a second source contact including a second conductive material, and (iv) a second drain contact including the second conductive material. In an example, the first and second conductive materials are compositionally different. In an example, the first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Willy Rachmady, Nitesh Kumar, Jami A. Wiedemer, Cheng-Ying Huang, Marko Radosavljevic, Mauro J. Kobrinsky, Patrick Morrow, Rohit Galatage, David N. Goldstein, Christopher J. Jezewski
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Patent number: 11830933Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.Type: GrantFiled: January 4, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros, Aaron Lilak, Patrick Morrow, Anh Phan, Cheng-Ying Huang, Ehren Mannebach
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Publication number: 20230377947Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.Type: ApplicationFiled: July 21, 2023Publication date: November 23, 2023Inventors: Cheng-Ying HUANG, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Ehren MANNEBACH, Patrick MORROW, Anh PHAN, Willy RACHMADY, Hui Jae YOO
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Publication number: 20230369399Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Ehren MANNEBACH, Anh PHAN, Aaron LILAK, Willy RACHMADY, Gilbert DEWEY, Cheng-Ying HUANG, Richard SCHENKER, Hui Jae YOO, Patrick MORROW
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Publication number: 20230352481Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor’s source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor’s channel region and extends downward into a recess that exposes the lower transistor’s source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor’s source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.Type: ApplicationFiled: July 7, 2023Publication date: November 2, 2023Inventors: Aaron D. LILAK, Gilbert DEWEY, Cheng-Ying HUANG, Christopher JEZEWSKI, Ehren MANNEBACH, Rishabh MEHANDRU, Patrick MORROW, Anand S. MURTHY, Anh PHAN, Willy RACHMADY