Abstract: A test clock generating apparatus is provided in the invention. The test clock generating apparatus includes an at-speed clock generator and a multiplexer. The at-speed clock generator is for receiving a reference clock signal and a scan chain enable signal and outputting an at-speed clock signal. The frequency of the at-speed clock signal is substantially the same with that of the reference clock signal. The multiplexer is for receiving the at-speed clock signal and a scan chain clock signal and outputting a test clock signal according to the scan chain enable signal. The frequency of the reference clock signal is higher than that of the scan chain clock.

Abstract: A logic system for performing scan test with single scan clock and related method. The logic system includes a first clock domain, which performs logic operations and scan tests with a first clock signal, and a second clock domain, which performs logic operations witha second clock signal and performs scan tests withthe first clock signal.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract: A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

Abstract: In the present invention a built in self test (BIST) for an embedded memory is described. The BIST can be used at higher levels of assembly and for commodity memories to perform functional and AC memory tests. A BIST controller comprising a finite state machine is used to step through a test sequence and control a sequence controller. The sequence controller provides data and timing sequences to the embedded memory to provide page mode and non-page mode tests along with a refresh test. The BIST logic is scan tested prior to performing the built in self test and accommodations for normal memory refresh is made throughout the testing. The BIST also accommodates a burn-in test where unique burn-in test sequences can be applied.