Patents by Inventor Chi Lin Teng
Chi Lin Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11315828Abstract: A method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group; performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen; partially etching the etch stop layer to expose the metal line; and forming a conductive feature above the etch stop layer and in physical contact with the metal line.Type: GrantFiled: June 25, 2019Date of Patent: April 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Fang Cheng, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
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Patent number: 11302798Abstract: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.Type: GrantFiled: May 29, 2020Date of Patent: April 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chi Chuang, Lin-Yu Huang, Chia-Hao Chang, Yu-Ming Lin, Ting-Ya Lo, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
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Publication number: 20210376111Abstract: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Cheng-Chi Chuang, Lin-Yu Huang, Chia-Hao Chang, Yu-Ming Lin, Ting-Ya Lo, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
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Patent number: 11049811Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.Type: GrantFiled: December 26, 2018Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao
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Publication number: 20210193566Abstract: Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.Type: ApplicationFiled: May 28, 2020Publication date: June 24, 2021Inventors: Ting-Ya Lo, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Shao-Kuan Lee, Cheng-Chin Lee
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Publication number: 20210193505Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.Type: ApplicationFiled: May 18, 2020Publication date: June 24, 2021Inventors: Hsin-Yen Huang, Chi-Lin Teng, Hai-Ching Chen, Shau-Lin Shue, Shao-Kuan Lee, Cheng-Chin Lee, Ting-Ya Lo
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Publication number: 20210134666Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.Type: ApplicationFiled: December 14, 2020Publication date: May 6, 2021Inventors: Hsin-Yen HUANG, Kai-Fang CHENG, Chi-Lin TENG, Shao-Kuan LEE, Hai-Ching CHEN
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Patent number: 10867847Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.Type: GrantFiled: July 30, 2018Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Shao-Kuan Lee, Hai-Ching Chen
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Publication number: 20200328152Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.Type: ApplicationFiled: June 26, 2020Publication date: October 15, 2020Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
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Patent number: 10700000Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.Type: GrantFiled: May 22, 2017Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
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Publication number: 20200058546Abstract: A method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group; performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen; partially etching the etch stop layer to expose the metal line; and forming a conductive feature above the etch stop layer and in physical contact with the metal line.Type: ApplicationFiled: June 25, 2019Publication date: February 20, 2020Inventors: Kai-Fang Cheng, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
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Publication number: 20190131240Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.Type: ApplicationFiled: December 26, 2018Publication date: May 2, 2019Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao
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Patent number: 10211097Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.Type: GrantFiled: March 7, 2016Date of Patent: February 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Shao-Kuan Lee, Hai-Ching Chen
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Patent number: 10163797Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.Type: GrantFiled: October 9, 2015Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao
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Publication number: 20180350669Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.Type: ApplicationFiled: July 30, 2018Publication date: December 6, 2018Inventors: Hsin-Yen HUANG, Kai-Fang CHENG, Chi-Lin TENG, Shao-Kuan LEE, Hai-Ching CHEN
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Patent number: 10090245Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.Type: GrantFiled: October 10, 2017Date of Patent: October 2, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Tien-I Bao, Jung-Hsun Tsai
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Publication number: 20180076132Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.Type: ApplicationFiled: November 13, 2017Publication date: March 15, 2018Inventors: Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao, Chien-Hua Huang
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Publication number: 20180033730Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.Type: ApplicationFiled: October 10, 2017Publication date: February 1, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Fang CHENG, Chi-Lin TENG, Hai-Ching CHEN, Hsin-Yen HUANG, Tien-I BAO, Jung-Hsun TSAI
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Patent number: 9859152Abstract: A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes determining a thickness of the protecting layer based on the expected concentration of metal ions. The method also includes forming the protecting layer at the determined thickness and in contact with the dielectric layer. The protecting layer can include at least one of silicon doped nitride, carbon nitride, silicon nitride, or silicon carbon.Type: GrantFiled: June 15, 2016Date of Patent: January 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
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Patent number: 9818690Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.Type: GrantFiled: October 30, 2015Date of Patent: November 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao, Chien-Hua Huang