Patents by Inventor Chi-Sung Oh
Chi-Sung Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110249483Abstract: A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.Type: ApplicationFiled: April 5, 2011Publication date: October 13, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chi-Sung Oh, Jin-Ho Kim, Ho-Cheol Lee, Uk-Song Kang, Hoon Lee
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Publication number: 20110242870Abstract: In one embodiment, the stacked memory includes a first group of stacked memory chips, a second group of stacked memory chips, and connection terminals configured to electrically connect a first memory chip among the stacked memory chips in the first group to a second memory chip among the stacked memory chips in the second group.Type: ApplicationFiled: January 17, 2011Publication date: October 6, 2011Applicant: Samsung Electronics Co., Ltd.Inventor: Chi Sung Oh
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Patent number: 8019948Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.Type: GrantFiled: October 21, 2010Date of Patent: September 13, 2011Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Chi-Sung Oh, Yong-Jun Kim, Kyung-Woo Nam, Jin-Kuk Kim, Soo-Young Kim
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Publication number: 20110193086Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.Type: ApplicationFiled: September 27, 2010Publication date: August 11, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Cheol LEE, Chi-Sung OH, Jin-Kuk KIM
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Publication number: 20110093235Abstract: A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.Type: ApplicationFiled: October 8, 2010Publication date: April 21, 2011Inventors: CHI-SUNG OH, Dong-Hyuk Lee, Ho-Cheol Lee, Jang-Woo Ryu, Jung-Bae Lee
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Patent number: 7929369Abstract: A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.Type: GrantFiled: April 30, 2009Date of Patent: April 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hyuk Lee, Chi-Sung Oh
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Publication number: 20110035544Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.Type: ApplicationFiled: October 21, 2010Publication date: February 10, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Chi-Sung OH, Yong-Jun KIM, Kyung-Woo NAM, Jin-Kuk KIM, Soo-Young KIM
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Publication number: 20110007576Abstract: Provided is a synchronous dynamic random access memory (DRAM) semiconductor device including multiple output buffers, a strobe control unit and multiple strobe buffers. Each of the output buffers is configured to output one bit of data. The strobe control unit is configured to output multiple strobe control signals in response to an externally input signal. The strobe buffers are connected to the output buffers and the strobe control unit, and each of the strobe buffers is configured to output at least one strobe signal. At least some of the strobe buffers are activated in response to the strobe control signals, and the output buffers are activated in response to the strobe signals output by the activated strobe buffers.Type: ApplicationFiled: February 9, 2010Publication date: January 13, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-kyu Kang, Ho-cheol Lee, Chi-sung Oh
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Patent number: 7840762Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.Type: GrantFiled: August 23, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., LtdInventors: Chi-Sung Oh, Yong-Jun Kim, Kyung-Woo Nam, Jin-Kuk Kim, Soo-Young Kim
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Publication number: 20100232213Abstract: Exemplary embodiments relate to a control signal driving device of a semiconductor device, including: a bus line; a converter receiving a first periodic control signal having the period (frequency) of a clock signal, converting the first periodic control signal into a converted control signal that has twice the period (half the frequency) of the clock signal, and outputting the converted control signal to the bus line; and a restoring unit connected to the opposite end of the bus line and receiving the converted control signal and restoring the converted control signal back into the first periodic control signal.Type: ApplicationFiled: February 24, 2010Publication date: September 16, 2010Inventors: Hyong-Ryol Hwang, Chi-Sung Oh, Sang-Kyu Kang
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Publication number: 20100177576Abstract: A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.Type: ApplicationFiled: January 13, 2010Publication date: July 15, 2010Inventors: Chi-Sung Oh, Jung-Bae Lee, Dong-Hyuk Lee
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Publication number: 20090296510Abstract: A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.Type: ApplicationFiled: April 30, 2009Publication date: December 3, 2009Inventors: Dong-Hyuk Lee, Chi-Sung Oh
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Patent number: 7596666Abstract: A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path accessible semiconductor memory device includes at least one shared memory area allocated in a memory cell array, operably connected to ports corresponding to a plurality of processors, each port used by the corresponding processor to selective access the shared memory area. The device further comprises an occupancy state signaling unit to output port occupancy state information to the processor requesting access to the shared memory area through the port used for the access request to indicate whether access to the shared memory area is allowed.Type: GrantFiled: August 22, 2006Date of Patent: September 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Joo Ahn, Chi-Sung Oh
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Patent number: 7586339Abstract: An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the method may include buffering output data in response to an output buffer enabling signal, transferring the buffered output data to an output node and initializing the output node of an output buffer in response to a triggering signal.Type: GrantFiled: May 10, 2006Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Chi-Sung Oh, Hyo-Joo Ahn
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Publication number: 20090106503Abstract: A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.Type: ApplicationFiled: October 23, 2007Publication date: April 23, 2009Inventors: Dong-Hyuk Lee, Kyung-Woo Nam, Yong-Jun Kim, Jong-Wook Park, Chi-Sung Oh
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Publication number: 20090059711Abstract: A multi-port memory device includes first and second ports, a first dedicated memory area assigned to the first port, a plurality of shared memory units having shared access by the first and second ports, a first set of I/O lines for the first dedicated memory area, and a second set of I/O lines for the shared memory units with the second set having more I/O lines than the first set. For example, the second set has N times more I/O lines than the first set, with N being a number of ports of the multi-port memory device or with N being a number of shared memory banks in a shared memory area.Type: ApplicationFiled: October 23, 2007Publication date: March 5, 2009Inventors: Chi-Sung Oh, Jung-Sik Kim
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Publication number: 20080170460Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.Type: ApplicationFiled: August 23, 2007Publication date: July 17, 2008Applicant: Samsung Electronics Co., LtdInventors: Chi-Sung OH, Yong-Jun Kim, Kyung-Woo Nam, Jin-Kuk Kim
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Patent number: 7394711Abstract: A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.Type: GrantFiled: December 27, 2006Date of Patent: July 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chi-Sung Oh, Ho-Cheol Lee, Nam-Jong Kim
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Publication number: 20070171755Abstract: A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.Type: ApplicationFiled: December 27, 2006Publication date: July 26, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Chi-Sung OH, Ho-Cheol Lee, Nam-Jong Kim
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Publication number: 20070150669Abstract: A multi-path accessible semiconductor memory device having a shared memory area in a DRAM memory cell array that can be randomly accessed by a plurality of processors is provided. The multi-path accessible semiconductor memory device includes at least one shared memory area allocated in a memory cell array, operably connected to ports corresponding to a plurality of processors, each port used by the corresponding processor to selective access the shared memory area. The device further comprises an occupancy state signaling unit to output port occupancy state information to the processor requesting access to the shared memory area through the port used for the access request to indicate whether access to the shared memory area is allowed.Type: ApplicationFiled: August 22, 2006Publication date: June 28, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Joo AHN, Chi-Sung OH