Abstract: An output circuit and method thereof. In an example, the output circuit may include an output buffer configured to buffer output data and to transfer the buffered output data to an output node, the output buffer initializing the output node in response to a triggering signal. In another example, the method may include buffering output data in response to an output buffer enabling signal, transferring the buffered output data to an output node and initializing the output node of an output buffer in response to a triggering signal.

Abstract: A semiconductor memory device for enhancing bitline precharge time and method for accelerating precharge time in the device is provided which may reduce overall precharging time, in an effort to guarantee proper high speed operations in the semiconductor memory device. In the method, an equalization enable signal may be applied to an equalizer of the device to precharge a bitline pair connected a memory cell, isolation part and sense amplifier of the device. Isolation control signals, to be applied to one or more of the isolation parts, may be delayed by a given time, so that a time of applying the isolation control signals is after a time of applying the equalization enable signal to the equalizer.

Abstract: A semiconductor memory device for enhancing bitline precharge time and method for accelerating precharge time in the device is provided which may reduce overall precharging time, in an effort to guarantee proper high speed operations in the semiconductor memory device. In the method, an equalization enable signal may be applied to an equalizer of the device to precharge a bitline pair connected a memory cell, isolation part and sense amplifier of the device. Isolation control signals, to be applied to one or more of the isolation parts, may be delayed by a given time, so that a time of applying the isolation control signals is after a time of applying the equalization enable signal to the equalizer.

Abstract: Boosted voltage generates and methods for an integrated circuit are configured to boost an initial boosted voltage to a first boosted voltage in response to detecting a drop in the initial voltage. The first boosted voltage is then boosted to a second boosted voltage in response to a pulse. The second boosted voltage is then repeatedly boosted to approach the initial boosted voltage in response to an oscillating signal. Accordingly, stable boosted voltages may be generated.

Abstract: Boosted voltage generates and methods for an integrated circuit are configured to boost an initial boosted voltage to a first boosted voltage in response to detecting a drop in the initial voltage. The first boosted voltage is then boosted to a second boosted voltage in response to a pulse. The second boosted voltage is then repeatedly boosted to approach the initial boosted voltage in response to an oscillating signal. Accordingly, stable boosted voltages may be generated.