Abstract: A key storage device comprising a first key unit and a second key unit is disclosed. The first key unit is configured to output a first logic value through, comprising: a first setting circuit configured to output a first setting voltage; and a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value. The second key unit is configured to output a second logic value through a second node, comprising: a second setting circuit configured to output a second setting voltage; and a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value. The absolute value of first threshold voltage is lower than which of the second threshold voltage. The first setting voltage is higher than the second setting voltage.

Abstract: An entropy source circuit, comprising: a first adjustable ring oscillator for operating under a first setting or a second setting according to a first control signal, for respectively generating a first oscillation clock signal and a second oscillation clock signal which have different frequencies under the first setting and the second setting; a first sampling circuit, for sampling the first oscillating clock signal according to the sampling frequency to generate first sampling values, or sampling the second oscillating clock signal according to the sampling frequency to generate second sampling values; a first detection circuit detecting a first distribution of the first sampling values; and a control circuit generating the first control signal to switch the first setting to the second setting when the first distribution does not meet a predetermined distribution. The entropy source circuit outputs entropy values according to the first sample value or the second sample value.

Abstract: A random number generator includes a static random number generator, a dynamic entropy source, a counter and a combining circuit. The static random number generator includes an initial random number pool and a static random number pool to output a static random number sequence from one thereof the initial random number pool and the static random number pool. The dynamic entropy source is used to generate a dynamic entropy bit. The counter is used to generate a dynamic random number sequence according to the dynamic entropy bit. The combining circuit is used to output a true random number sequence to a lively random number pool according to the static random number sequence and the dynamic random number sequence. The static random number pool is updated when the lively random number pool is fully updated.

Abstract: An entropy source circuit is provided. The entropy source circuit includes a digital circuit, a determination circuit and a time-to-digital converter (TDC), wherein the determination circuit is coupled to the digital circuit, and the TDC is coupled to the determination circuit. The digital circuit is configured to generate result data at a second time point according to input data received at a first time point, and the determination circuit is configured to perform determination on reference data with dynamic output generated by the digital circuit, to generate a determination result, wherein the reference data is equal to the result data. In addition, the TDC is configured to perform a time-to-digital conversion on a delay of the digital circuit for generating the result data according to the input data with aid of the determination signal, in order to generate entropy data corresponding to the delay.

Abstract: An entropy generator includes a physically unclonable function, a dynamic entropy source and an entropy enhancement engine. The physically unclonable function is used to provide a truly random static entropy. The dynamic entropy source is used to generate a dynamic entropy. The entropy enhancement engine is coupled to the physically unclonable function and the dynamic entropy source, and is used to generate an enhanced entropy according to the truly random static entropy and the dynamic entropy. The expected hamming distance is an expected value of a hamming distance between a truly random static entropy and another truly random static entropy provided by a physically unclonable function (PUF).

Abstract: A built-in self-test (BIST) circuit and a BIST method for Physical Unclonable Function (PUF) quality check are provided. The BIST circuit may include a PUF array, a readout circuit coupled to the PUF array, and a first comparing circuit coupled to the readout circuit. The PUF array may include a plurality of PUF units, wherein each of the PUF units includes a first cell and a second cell. The readout circuit may be configured to output an output bit from the first cell and output a parity bit from the second cell. The first comparing circuit may be configured to compare an output string with a parity string to generate a parity check result, wherein the output string includes output bits respectively read from selected PUF units of the PUF units, and the parity string includes parity bits read from the selected PUF units.

Abstract: A key storage device comprising a first key unit and a second key unit is disclosed. The first key unit is configured to output a first logic value through, comprising: a first setting circuit configured to output a first setting voltage; and a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value. The second key unit is configured to output a second logic value through a second node, comprising: a second setting circuit configured to output a second setting voltage; and a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value. The absolute value of first threshold voltage is lower than which of the second threshold voltage. The first setting voltage is higher than the second setting voltage.

Abstract: A random number generator and a random number generating method are provided. The random number generator includes a first stage generator and a second stage generator. The first stage generator outputs a first random number and a second random number at a first time point and a second time point, respectively. The second stage generator generates a final output at least according to the first random number. More particularly, the second stage generator includes a reseed circuit for generating a reseed signal, to control whether to generate the final output according to the second random number. In addition, when the second stage generator generates the final output at a current data cycle without using the second random number, the first stage generator holds the second random number for generating the final output at a next data cycle.

Abstract: A built-in self-test (BIST) circuit and a BIST method for Physical Unclonable Function (PUF) quality check are provided. The BIST circuit may include a PUF array, a readout circuit coupled to the PUF array, and a first comparing circuit coupled to the readout circuit. The PUF array may include a plurality of PUF units, wherein each of the PUF units includes a first cell and a second cell. The readout circuit may be configured to output an output bit from the first cell and output a parity bit from the second cell. The first comparing circuit may be configured to compare an output string with a parity string to generate a parity check result, wherein the output string includes output bits respectively read from selected PUF units of the PUF units, and the parity string includes parity bits read from the selected PUF units.

Abstract: A random number generator includes a counting value generator, an address generator, a static entropy source and a processing circuit. The counting value generator generates a first random number. The address generator generates an address signal. The static entropy source is connected with the address generator to receive the address signal and generates a second random number. The processing circuit is connected with the static entropy source and the counting value generator to receive the first random number and the second random number. After the first random number and the second random number are processed by the processing circuit, the processing circuit generates an output random number.

Abstract: A random number generator includes a static random number generator, a dynamic entropy source, a counter and a combining circuit. The static random number generator includes an initial random number pool and a static random number pool to output a static random number sequence from one thereof the initial random number pool and the static random number pool. The dynamic entropy source is used to generate a dynamic entropy bit. The counter is used to generate a dynamic random number sequence according to the dynamic entropy bit. The combining circuit is used to output a true random number sequence to a lively random number pool according to the static random number sequence and the dynamic random number sequence. The static random number pool is updated when the lively random number pool is fully updated.

Abstract: An entropy generator includes a static entropy source, a dynamic entropy source and an entropy enhancement engine. The static entropy source is used to provide a truly random static entropy. The dynamic entropy source is used to generate a dynamic entropy. The entropy enhancement engine is coupled to the static entropy source and the dynamic entropy source, and is used to generate an enhanced entropy according to the truly random static entropy and the dynamic entropy.

Abstract: A random number generator includes a counting value generator, an address generator, a static entropy source and a processing circuit. The counting value generator generates a first random number. The address generator generates an address signal. The static entropy source is connected with the address generator to receive the address signal and generates a second random number. The processing circuit is connected with the static entropy source and the counting value generator to receive the first random number and the second random number. After the first random number and the second random number are processed by the processing circuit, the processing circuit generates an output random number.

Abstract: A random code generator includes a control circuit, a high voltage power supply, a memory module and a counter. The control circuit generates a control signal and an enabling signal. During a program cycle, the enabling signal is activated. The high voltage power supply receives the enabling signal. A charge pump of the high voltage power supply generates a program voltage according to an oscillation signal. When the enabling signal is activated, the high voltage power supply outputs the program voltage. The memory module determines a selected memory cell of the memory module according to the control signal. During the program cycle, the selected memory cell receives the program voltage. During the program cycle, the counter counts a pulse number of the oscillation signal to acquire a counting value, and the control circuit determines a random code according to the counting value.

Abstract: A random code generator includes a control circuit, a high voltage power supply, a memory module and a counter. The control circuit generates a control signal and an enabling signal. During a program cycle, the enabling signal is activated. The high voltage power supply receives the enabling signal. A charge pump of the high voltage power supply generates a program voltage according to an oscillation signal. When the enabling signal is activated, the high voltage power supply outputs the program voltage. The memory module determines a selected memory cell of the memory module according to the control signal. During the program cycle, the selected memory cell receives the program voltage. During the program cycle, the counter counts a pulse number of the oscillation signal to acquire a counting value, and the control circuit determines a random code according to the counting value.

Abstract: A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit.

Abstract: A power system with detecting function includes a power source, a power level detector, and a power floating detector. The power source includes multiple voltage sources for operations in multiple voltage domains, respectively. The power level detector is configured to constantly monitor the voltage level of each voltage domain. The power floating detector is configured to detect the presence of floating voltages in each voltage domain. Therefore, the present power system with detection function can guarantee stable operations and detect glitch attacks.

Abstract: A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit.

Abstract: A power system with detecting function includes a power source, a power level detector, and a power floating detector. The power source includes multiple voltage sources for operations in multiple voltage domains, respectively. The power level detector is configured to constantly monitor the voltage level of each voltage domain. The power floating detector is configured to detect the presence of floating voltages in each voltage domain. Therefore, the present power system with detection function can guarantee stable operations and detect glitch attacks.

Abstract: The invention provides a memory apparatus, a charge pump circuit, and a voltage pumping method thereof. The charge pump circuit including a plurality of delay units, a latch circuit, and a plurality of charge pump units. The delay units respectively generate a plurality clock signals according to an output clock signal. The latch circuit receive a final stage clock signal of the clock signals and a latch enable signal. The latch circuit decides whether to latch final stage clock signal or not to generate the output clock signal according to the latch enable signal. The first stage of the charge pump unit receives an input voltage, and the charge pump units operate a voltage pumping operation on the input voltage to generate an output voltage according to the clock signals and the output clock signal.