Patents by Inventor Chia-Cheng Lin
Chia-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153887Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.Type: ApplicationFiled: January 4, 2024Publication date: May 9, 2024Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
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Publication number: 20240155185Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.Type: ApplicationFiled: November 9, 2022Publication date: May 9, 2024Inventors: Chia-Hao CHANG, You-Tsai JENG, Kai-Wen YEH, Yi-Cheng CHEN, Te-Chuan WANG, Kai-Wen CHENG, Chin-Lung LIN, Tai-Lai TUNG, Ko-Yin LAI
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Patent number: 11980037Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.Type: GrantFiled: June 19, 2020Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Jack T. Kavalieros, Uygar E. Avci, Chia-Ching Lin, Seung Hoon Sung, Ashish Verma Penumatcha, Ian A. Young, Devin R. Merrill, Matthew V. Metz, I-Cheng Tung
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Publication number: 20240141703Abstract: A vehicle door lock assembly includes a housing, a first locking assembly, a second locking assembly, a driving module and a micro switch. The first locking assembly includes an inner handle, an outer handle and a first lock tongue. The inner handle and the outer handle are disposed on the housing and respectively control the first lock tongue to move. The second locking assembly includes a second lock and a second lock tongue including a first segment and a second segment slidably connected with each other. The second lock includes a mandrel having an assembling portion. The driving module includes a motor assembled with the mandrel, and the second segment is moved when the motor drives the mandrel to rotate. The micro switch includes an inductive element, and the assembling portion has an inductive portion.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventor: CHIA-CHENG LIN
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Publication number: 20240141707Abstract: A vehicle door lock assembly includes a housing, a first locking assembly and a second locking assembly. The first locking assembly includes an inner handle, an outer handle, a first lock and a first lock tongue. The first lock tongue has a tendency to move outward of the housing, and the inner and outer handles respectively control the first lock tongue to move inward of the housing. The first lock is connected with a first blocking member. The second locking assembly includes a control member, a second lock and a second lock tongue. The second lock is connected with a second blocking member, and the second lock and the control member are co-movable. The second lock drives the second lock tongue to move outward of the housing when locked, and the second lock drives the second lock tongue to move inward of the housing when unlocked.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventor: CHIA-CHENG LIN
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Patent number: 11968840Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.Type: GrantFiled: November 10, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11966546Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.Type: GrantFiled: August 19, 2021Date of Patent: April 23, 2024Assignee: E Ink Holdings Inc.Inventors: Chen-Cheng Lin, Chia-I Liu, Kun-Hsien Lee, Hung-Wei Tseng
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Patent number: 11964299Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.Type: GrantFiled: October 26, 2021Date of Patent: April 23, 2024Assignee: FOREMOST GOLF MFG. LTD.Inventors: Chia-Sheng Huang, Chi-Ling Lin, Chia-Cheng Wu, Ching-Hsiang Liu
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Patent number: 11967272Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.Type: GrantFiled: December 9, 2022Date of Patent: April 23, 2024Assignees: AUO Corporation, National Cheng-Kung UniversityInventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
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Publication number: 20240124844Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.Type: ApplicationFiled: October 4, 2023Publication date: April 18, 2024Inventors: Chia-Hsin Lee, Po-Cheng Lin, Yong-Cheng Kao, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
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Patent number: 11962847Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.Type: GrantFiled: November 9, 2022Date of Patent: April 16, 2024Assignee: MEDIATEK INC.Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
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Patent number: 11961892Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20240117314Abstract: The present invention relates to a method for preparing a modified stem cell, including the following steps: a cell culture step: culturing stem cells in a first culture medium of a culture dish at a predetermined cell density, and removing the first culture medium after a first culture time to obtain a first cell intermediate; an activity stimulation step: preserving the first cell intermediate in a freezing container having a cell cryopreservation solution, and performing a constant temperature stimulation treatment or a variable temperature stimulation treatment for at least more than 1 day; and a product collection step: after completing the activity stimulation step, placing the freezing container in an environment at a thawing temperature for thawing, and then removing the cell cryopreservation solution to obtain the modified stem cell. The modified stem cell can release at least one or more of IL-4, IL-5, IL-13, G-CSF, Fractalkine, and EGF.Type: ApplicationFiled: October 3, 2023Publication date: April 11, 2024Inventors: Ruei-Yue Liang, Chia-Hsin Lee, Kai-Ling Zhang, Po-Cheng Lin, Ming-Hsi Chuang, Yu-Chen Tsai, Peggy Leh Jiunn Wong
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Publication number: 20240115616Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.Type: ApplicationFiled: October 4, 2023Publication date: April 11, 2024Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
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Publication number: 20240120236Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.Type: ApplicationFiled: April 25, 2023Publication date: April 11, 2024Inventors: Tai-Jung Kuo, Po-Cheng Shih, Wan Chen Hsieh, Zhen-Cheng Wu, Chia-Hui Lin, Tze-Liang Lee
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Patent number: 11952662Abstract: Disclosed is a powder atomic layer deposition equipment with a quick release function, comprising a vacuum chamber, a shaft sealing device, and a driving unit connected to the shaft sealing device. The vacuum chamber is connected to the shaft sealing device, and an enclosed space is formed between the vacuum chamber and the shaft sealing device. At least one air extraction line is located in the shaft sealing device and fluidly connected to the enclosed space, the air extraction line being used in pumping gas out from the enclosed space to fix the vacuum chamber to the shaft sealing device so that the drive unit rotates the vacuum chamber via the shaft sealing device to facilitate the formation of a uniform thin film on powder surface. When the pumping stops, the vacuum chamber can be quickly released from the shaft sealing device to improve the process efficiency and convenience of use.Type: GrantFiled: October 18, 2021Date of Patent: April 9, 2024Assignee: SKY TECH INC.Inventors: Jing-Cheng Lin, Jung-Hua Chang, Chia-Cheng Ku
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Patent number: 11947217Abstract: A backlight module including a light guide plate, a light source, a diffuse reflector and a light-splitting film is provided. The light guide plate has a light incident surface, and a light-emitting surface and a bottom surface which are respectively connected to the light incident surface and opposite to each other. The light source is disposed on one side of the light incident surface of the light guide plate. The diffuse reflector is disposed on one side of the bottom surface of the light guide plate. The light-splitting film is disposed between the light guide plate and the diffuse reflector. The light-splitting film has a substrate and a plurality of first optical microstructures disposed on one side of the substrate. An extending direction of the first optical microstructures intersects with the light incident surface of the light guide plate. A display apparatus using the backlight module is also provided.Type: GrantFiled: October 23, 2022Date of Patent: April 2, 2024Assignee: Coretronic CorporationInventors: Tzeng-Ke Shiau, Yi-Cheng Lin, Chia-Liang Kang
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Patent number: 11948895Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.Type: GrantFiled: July 4, 2022Date of Patent: April 2, 2024Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
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Publication number: 20240105601Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Wei-An LAI, Te-Hsin CHIU, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG, Chia-Tien WU