Patents by Inventor Chia-Cheng Lin
Chia-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Patent number: 11947217Abstract: A backlight module including a light guide plate, a light source, a diffuse reflector and a light-splitting film is provided. The light guide plate has a light incident surface, and a light-emitting surface and a bottom surface which are respectively connected to the light incident surface and opposite to each other. The light source is disposed on one side of the light incident surface of the light guide plate. The diffuse reflector is disposed on one side of the bottom surface of the light guide plate. The light-splitting film is disposed between the light guide plate and the diffuse reflector. The light-splitting film has a substrate and a plurality of first optical microstructures disposed on one side of the substrate. An extending direction of the first optical microstructures intersects with the light incident surface of the light guide plate. A display apparatus using the backlight module is also provided.Type: GrantFiled: October 23, 2022Date of Patent: April 2, 2024Assignee: Coretronic CorporationInventors: Tzeng-Ke Shiau, Yi-Cheng Lin, Chia-Liang Kang
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Patent number: 11948895Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.Type: GrantFiled: July 4, 2022Date of Patent: April 2, 2024Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
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Publication number: 20240105601Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Wei-An LAI, Te-Hsin CHIU, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG, Chia-Tien WU
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Patent number: 11942380Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.Type: GrantFiled: October 26, 2020Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
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Publication number: 20240094625Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Chih-Cheng LIN, Chia-Jen CHEN
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Publication number: 20240088195Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
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Publication number: 20240088307Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Publication number: 20240088246Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
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Patent number: 11929318Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.Type: GrantFiled: May 10, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Patent number: 11929417Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 30, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20240075071Abstract: Disclosed in the present invention is an optimized cell transplant. The optimized cell transplant is formed by performing gene induction and modification on a mesenchymal stem cell in the form of a small molecule and protein composition. The expression levels of CD200 gene, Galectin-9 gene and VISTA gene can be increased synchronously after cell culture. Vector virus infection and plasmid transfection are not required in the cell preparation process, so that high biological safety and great clinical application value of cells are achieved.Type: ApplicationFiled: November 23, 2022Publication date: March 7, 2024Inventors: Ruei-Yue Liang, Kai-Ling Zhang, Ming-Hsi Chuang, Po-Cheng Lin, Peggy Leh Jiunn Wong, Chia-Hsin Lee
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Patent number: 11921314Abstract: A backlight module includes a light guide plate, a light source, and an optical film. The light guide plate has a light incident surface and a light exiting surface opposite to the light incident surface, in which the light exiting surface has a normal line. The light source is adjacent to the light incident surface. The optical film is disposed to the light exiting surface and includes plural parallel prisms and plural microstructures. An extending direction of each of the prisms is perpendicular to the normal line, and each of the prisms faces the light exiting surface of the light guide plate. Each of the microstructures is located on a surface of the optical film which faces away from the light guide plate. Each of the microstructures has a pyramid structure with plural facets. The prisms are located between the microstructures and the light exiting surface.Type: GrantFiled: March 24, 2023Date of Patent: March 5, 2024Assignee: Radiant Opto-Electronics CorporationInventors: Chia-Yin Chang, Po-Chang Huang, Kun-Cheng Lin
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Patent number: 11915977Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: April 12, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Patent number: 11917230Abstract: A system and method for maximizing bandwidth in an uplink for a 5G communication system is disclosed. Multiple end devices generate image streams. A gateway is coupled to the end devices. The gateway includes a gateway monitor agent collecting utilization rate data of the gateway and an image inspector collecting inspection data from the received image streams. An edge server is coupled to the gateway. The edge server includes an edge server monitor agent collecting utilization rate data of the edge server. An analytics manager is coupled to the gateway and the edge server. The analytics manager is configured to determine an allocation strategy based on the collected utilization rate data from the gateway and the edge server.Type: GrantFiled: October 6, 2021Date of Patent: February 27, 2024Assignee: Quanta Cloud Technology Inc.Inventors: Yi-Neng Zeng, Keng-Cheng Liu, Wei-Ming Huang, Shih-Hsun Lai, Ji-Jeng Lin, Chia-Jui Lee, Liao Jin Xiang
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Patent number: 11911951Abstract: A matte film for hot pressing and a manufacturing method thereof are provided. The manufacturing method includes steps of forming at least one polyester composition into an unstretched polyester thick film and stretching the unstretched polyester thick film in a machine direction (MD) and a transverse direction (TD). The polyester composition includes 81% to 97.9497% by weight of a polyester resin, 0.02% to 2% by weight of an antioxidative ingredient, 0.0003% to 1% by weight of a nucleating agent, 0.01% to 2% by weight of a flow aid, 0.01% to 2% by weight of a polyester modifier, 0.01% to 2% by weight of an inorganic filler, and 2% to 10% by weight of silica particles. The polyester resin has an intrinsic viscosity between 0.60 dl/g and 0.80 dl/g.Type: GrantFiled: September 4, 2020Date of Patent: February 27, 2024Assignee: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Wen-Cheng Yang, Wen-Jui Cheng, Chia-Yen Hsiao, Chien-Chih Lin
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Publication number: 20240054974Abstract: In examples, an electronic device comprises a bus and a microcontroller coupled to the bus. The microcontroller is to encode a pattern in a pulse width modulated (PWM) signal by manipulating a duty cycle of the PWM signal and a duration of the duty cycle and to provide the PWM signal on the bus. The electronic device comprises a display panel and a timing controller (TCON) coupled to the display panel and to the microcontroller via the bus. The TCON is to control a brightness feature and a non-brightness feature of the display panel based on the pattern encoded in the PWM signal.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Inventors: Chia-Cheng LIN, Thong THAI, Super LIAO, Chen-Mu CHANG
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Publication number: 20230401296Abstract: In an example in accordance with the present disclosure, a wearable extended reality (XR) system is described. The wearable XR system includes a transceiver to receive, from a host computing device, a hologram pattern of original content to be displayed. The wearable XR system also includes a display unit. The display unit includes 1) a pattern lens to display the hologram pattern in front of a red, green, blue (RGB) light source and 2) the RGB light source to emit red, green, and blue light towards the hologram pattern to deconstruct the hologram pattern to present the original content. The wearable XR system also includes an image director to reflect the decoded original content towards a user of the wearable XR system.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Super Liao, Chia-Cheng Lin, Hsing-Hung Hsieh
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Publication number: 20230359775Abstract: In an example in accordance with the present disclosure, a compute device is described. The compute device includes a host controller to 1) receive identification data of peripheral devices coupled to a computing dock and 2) compare the identification data with values stored in a database. A stored value indicates a combination of peripheral devices previously coupled to the computing dock. The compute device also includes a device connection controller to, responsive to the identification data matching a stored value, retrieve operational data for the peripheral devices from the database. The device connection controller is also to connect the compute device with the peripheral devices based on operational data retrieved from the database.Type: ApplicationFiled: September 30, 2020Publication date: November 9, 2023Applicant: Hewlett-Packard Development Company, L.P.Inventors: Tsue-Yi Huang, Kang-Ning Feng, Chia-Cheng Lin, Chao-Shen Chen
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Publication number: 20230237153Abstract: An example computing device comprises: a media capture device to capture media; a pin coupled to the media capture device to communicate an unlock signal to the media capture device; and a basic input/output system interconnected with the pin, wherein, to control activation of the media capture device, the basic input/output system is to: store an authentication parameter, receive, from the media capture device, an unlock request; in response to the unlock request, verify an authentication input against the authentication parameter, and in response to a successful verification, send the unlock signal to unlock the media capture device via the pin.Type: ApplicationFiled: July 22, 2020Publication date: July 27, 2023Applicant: Hewlett-Packard Development Company, L.P.Inventors: YI-FAN HSIA, CHIH-KAI CHANG, HUNG-LUNG CHEN, CHIA-CHENG LIN, HSIN-JEN LIN, HENG-FU CHANG