Patents by Inventor Chia-hao Lee
Chia-hao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9985019Abstract: A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region. A first well is in the substrate. The first well substantially contacts a side of the first light doping region and does not extend under the first light doping region. The conductive type of the first well is opposite that of the first light doping region. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region is disposed in the first well and the first light doping region at two sides of the first gate stack. The conductive type of the first heavy doping region is opposite that of the first light doping region.Type: GrantFiled: September 16, 2015Date of Patent: May 29, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Jun-Wei Chen
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Patent number: 9978864Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: December 3, 2015Date of Patent: May 22, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tse-Hsiao Liu, Sing-Lin Wu, Chung-Hsuan Wang, Yung-Lung Chou, Chia-Hao Lee, Chih-Cherng Liao
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Patent number: 9978867Abstract: A semiconductor substrate structure includes a substrate having a first conductivity type, an oxide layer disposed on the substrate, and a semiconductor layer disposed on the oxide layer. The semiconductor substrate structure also includes a first buried layer disposed in the semiconductor layer, having a second conductivity type opposite to the first conductivity type. The semiconductor substrate structure further includes a second buried layer disposed in the semiconductor layer and above the first buried layer, having the first conductivity type, wherein the first buried layer and the second buried layer are separated by a distance.Type: GrantFiled: November 8, 2016Date of Patent: May 22, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Pei-Heng Hung, Manoj Kumar, Chia-Hao Lee
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Publication number: 20180130907Abstract: A semiconductor substrate structure includes a substrate having a first conductivity type, an oxide layer disposed on the substrate, and a semiconductor layer disposed on the oxide layer. The semiconductor substrate structure also includes a first buried layer disposed in the semiconductor layer, having a second conductivity type opposite to the first conductivity type. The semiconductor substrate structure further includes a second buried layer disposed in the semiconductor layer and above the first buried layer, having the first conductivity type, wherein the first buried layer and the second buried layer are separated by a distance.Type: ApplicationFiled: November 8, 2016Publication date: May 10, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Pei-Heng HUNG, Manoj KUMAR, Chia-Hao LEE
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Patent number: 9929283Abstract: A semiconductor device includes a semiconductor substrate, a first well region, and a second well region. The semiconductor substrate has a first conductivity type. The first and second well regions are disposed in the semiconductor substrate. The first and second well regions have a second conductivity type that is opposite to the first conductivity type. The semiconductor device also includes a first top layer and a second top layer. The first top layer is disposed in the semiconductor substrate. The first top layer extends from the first well region to the second well region. The first top layer has the first conductivity type. The second top layer is disposed in the semiconductor substrate and on the first top layer. The second top layer extends from the first well region to the second well region. The second top layer has the second conductivity type.Type: GrantFiled: March 6, 2017Date of Patent: March 27, 2018Assignee: Vanguard International Semiconductor CorporationInventors: Manoj Kumar, Wen-Hsin Lin, Shin-Cheng Lin, Chia-Hao Lee, Chih-Cherng Liao
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Patent number: 9898319Abstract: A method for live migrating a virtual machine includes connecting to a virtual machine operated in a first host by a client; transmitting condition data of the virtual machine to a second host by the first host during a transmitting time, the first host and the second host being located at different net domains; transmitting a variance of condition data of the virtual machine generated in the transmitting time to the second host by the first host; providing a notification to the client to reconnect to the second host by the first host; modifying a network packets transmitting rule by the client based on the notification of the first host, and activating the virtual machine by the second host based on the condition data of the virtual machine and the variance of the condition data of the virtual machine thereby maintaining the connection between the client and the virtual machine.Type: GrantFiled: June 9, 2015Date of Patent: February 20, 2018Assignee: National Central UniversityInventors: Fu-Hau Hsu, Tzung-Ting Lin, Wei-Tai Cai, Chia-Hao Lee
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Patent number: 9773681Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer disposed over the substrate; a gate electrode disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate electrode; a trench extending from a top surface of the epitaxial layer through the source region into the epitaxial layer, wherein the trench has a slanted side and a bottom surface; and a first conductive-type linking region having the first conductive type, wherein the first conductive-type linking region surrounds the slanted side of the trench and contacts the bottom surface of the trench, wherein the first conductive-type linking region electrically connects the source region and the substrate. The present disclosure also provides a method for manufacturing this semiconductor device.Type: GrantFiled: June 5, 2015Date of Patent: September 26, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Manoj Kumar, Tsung-Hsiung Lee, Pei-Heng Hung, Chia-Hao Lee, Jui-Chun Chang
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Patent number: 9748339Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereon; a first well region disposed in a portion of the semiconductor layer; a second well region disposed in another portion of the semiconductor layer; a pair of third well regions disposed in a portion of the semiconductor layer at opposite sides of the second well region; a plurality of isolation elements disposed over the semiconductor layer, respectively between the third well regions and the first and second well region; a deep well region disposed in a portion of the semiconductor substrate adjacent to the semiconductor layer between the first and second well region; a first doping region disposed in the first well region; and second doping regions disposed in the third well regions.Type: GrantFiled: January 6, 2017Date of Patent: August 29, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Pei-Heng Hung, Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao
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Patent number: 9697806Abstract: A self-refresh control method for a display system includes receiving a frame from a video source of the display system; storing the frame in a storage module of the display system according to a writing timing sequence signal; accessing data stored in the storage module as a self-refresh frame according to a reading timing sequence, for outputting the self-refresh frame to a display device of the display system; and adjusting the reading timing sequence signal according to the writing timing sequence signal and the reading timing sequence signal.Type: GrantFiled: May 8, 2014Date of Patent: July 4, 2017Assignee: NOVATEK Microelectronics Corp.Inventors: Chia-Hao Lee, Yu-Hsuan Huang, Chueh-An Tsai
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Publication number: 20170162691Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Tse-Hsiao LIU, Sing-Lin WU, Chung-Hsuan WANG, Yung-Lung CHOU, Chia-Hao LEE, Chih-Cherng LIAO
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Patent number: 9666699Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.Type: GrantFiled: March 30, 2016Date of Patent: May 30, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Pei-Heng Hung, Manoj Kumar, Hsiung-Shih Chang, Chia-Hao Lee, Jun-Wei Chen
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Patent number: 9646964Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.Type: GrantFiled: July 23, 2015Date of Patent: May 9, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Manoj Kumar, Pei-Heng Hung, Hsiung-Shih Chang, Chia-Hao Lee, Jui-Chun Chang
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Publication number: 20170117408Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.Type: ApplicationFiled: October 22, 2015Publication date: April 27, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Hung LIN, Chia-Hao LEE, Chih-Cherng LIAO
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Patent number: 9614078Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.Type: GrantFiled: October 22, 2015Date of Patent: April 4, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Hung Lin, Chia-Hao Lee, Chih-Cherng Liao
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Publication number: 20170077091Abstract: A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region. A first well is in the substrate. The first well substantially contacts a side of the first light doping region and does not extend under the first light doping region. The conductive type of the first well is opposite that of the first light doping region. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region is disposed in the first well and the first light doping region at two sides of the first gate stack. The conductive type of the first heavy doping region is opposite that of the first light doping region.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Manoj KUMAR, Chia-Hao LEE, Chih-Cherng LIAO, Jun-Wei CHEN
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Publication number: 20170025411Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.Type: ApplicationFiled: July 23, 2015Publication date: January 26, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Manoj KUMAR, Pei-Heng HUNG, Hsiung-Shih CHANG, Chia-Hao LEE, Jui-Chun CHANG
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Patent number: 9553091Abstract: A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of the first well, wherein the conductive type of the first well and the conductive type of the first light-doping region are opposite. The first high-voltage MOS device region also includes a first gate stack on a part of the first well and a part of the first light-doping region, and first heavy-doping regions in the first well and the first light-doping region at two sides of the gate stack, wherein the conductive type of the first heavy-doping region and the conductive type of the first well are the same. The first light-doping region between the first well and the first heavy-doping regions is a channel region of the first high-voltage MOS device region.Type: GrantFiled: September 23, 2015Date of Patent: January 24, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Ching-Yi Hsu, Jun-Wei Chen
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Patent number: 9548354Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A polysilicon layer having the first conductivity type fills the trench, and a first doping region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and on sidewalls of the trench. A method for forming the semiconductor device is also provided.Type: GrantFiled: December 17, 2015Date of Patent: January 17, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Chia-Hao Lee, Po-Heng Lin, Chih-Cherng Liao, Jun-Wei Chen
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Patent number: 9548375Abstract: A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other in the high-voltage N-type well region. The vertical diode also includes an N-type well region in the high-voltage N-type well region, and an N-type heavily doped region in the N-type well region. A plurality of isolation structures are formed on the substrate to define an anode region and a cathode region. There is a bottom N-type implanted region under the high-voltage N-type well region corresponding to the anode region. The bottom N-type implanted region directly contacts or partially overlaps the high-voltage N-type well region. A method for fabricating a vertical diode is also provided.Type: GrantFiled: September 28, 2016Date of Patent: January 17, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Hsiung-Shih Chang, Manoj Kumar, Jui-Chun Chang, Chia-Hao Lee, Li-Che Chen
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Patent number: 9530900Abstract: A Schottky diode is provided, which includes a well of a first conductive type and a lightly doped region of a second conductive type on the well, wherein the first conductive type is opposite to the second conductive type. The Schottky diode includes a heavily doped region of the second conductive type on the well, and a gate structure on a part of the lightly doped region. The gate structure includes a gate electrode and a gate dielectric layer. The lightly doped region not covered by the gate structure and the heavily doped region are disposed at two opposite sides of the gate structure, respectively. The Schottky diode includes a first contact electrically connecting the heavily doped region and a first electrode, a second contact electrically connecting the gate electrode and a second electrode, and a third contact electrically connecting the lightly doped region and the second electrode.Type: GrantFiled: January 26, 2016Date of Patent: December 27, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Pei-Heng Hung, Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Jun-Wei Chen