Patents by Inventor Chia-hao Lee

Chia-hao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9478644
    Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well region having the first conduction type is disposed in the semiconductor layer. A second well and a third well having a second conduction type are disposed to opposite sides of the first well region. The second well and the third well are separated from the first well region. A first anode doped region is disposed in the second well. A second anode doped region and a third anode doped region having the first conduction type are disposed in the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: October 25, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Pei-Heng Hung, Manoj Kumar, Hsiung-Shih Chang, Chia-Hao Lee, Jui-Chun Chang
  • Patent number: 9466730
    Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 11, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Rahul Kumar, Manoj Kumar, Gene Sheu, Shao-Ming Yang, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
  • Publication number: 20160239329
    Abstract: A method for live migrating a virtual machine includes connecting to a virtual machine operated in a first host by a client; transmitting condition data of the virtual machine to a second host by the first host during a transmitting time, the first host and the second host being located at different net domains; transmitting a variance of condition data of the virtual machine generated in the transmitting time to the second host by the first host; providing a notification to the client to reconnect to the second host by the first host; modifying a network packets transmitting rule by the client based on the notification of the first host, and activating the virtual machine by the second host based on the condition data of the virtual machine and the variance of the condition data of the virtual machine thereby maintaining the connection between the client and the virtual machine.
    Type: Application
    Filed: June 9, 2015
    Publication date: August 18, 2016
    Inventors: Fu-Hau HSU, Tzung-Ting LIN, Wei-Tai CAI, Chia-Hao LEE
  • Patent number: 9318601
    Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 19, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Pei-Heng Hung, Priyono Tri Sulistyanto, Chia-Hao Lee, Chih-Cherng Liao, Shang-Hui Tu
  • Publication number: 20160064573
    Abstract: An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulator formed on a top surface of a semiconductor substrate. The semiconductor device also includes a semiconductor layer containing a first region of a first conductivity type and formed on the insulator layer. The first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer. The semiconductor device further includes a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region. The second region has a doping concentration heavier than that of the first region. In addition, the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Priyono Tri SULISTYANTO, Manoj KUMAR, Chia-Hao LEE, Chih-Cherng LIAO, Shang-Hui TU
  • Patent number: 9263574
    Abstract: A semiconductor device includes a semiconductor layer formed over a semiconductor substrate. A well region is disposed in a portion of the semiconductor layer, and a plurality of first doped regions is disposed in various portions of the well region. A second doped region is disposed in a portion of the well region. An isolation element is disposed in a portion of the top-most one of the first doped regions, and a third doped region is disposed in a portion of the top-most one of the first doped regions. A fourth doped region is disposed in a portion of the second doped region. An insulating layer overlies the third doped region, the isolation element, the second doped region, and the fourth doped region, and a conductive layer overlies the insulating layer.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: February 16, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Pei-Heng Hung, Chia-Hao Lee, Chih-Cherng Liao, Shang-Hui Tu
  • Patent number: 9263436
    Abstract: A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: February 16, 2016
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsiung-Shih Chang, Jui-Chun Chang, Shang-Hui Tu, Priyono Tri Sulistyanto, Chia-Hao Lee
  • Publication number: 20150357466
    Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 10, 2015
    Inventors: Manoj KUMAR, Pei-Heng HUNG, Priyono Tri SULISTYANTO, Chia-Hao LEE, Chih-Cherng LIAO, Shang-Hui TU
  • Publication number: 20150325166
    Abstract: A self-refresh control method for a display system includes receiving a frame from a video source of the display system; storing the frame in a storage module of the display system according to a writing timing sequence signal; accessing data stored in the storage module as a self-refresh frame according to a reading timing sequence, for outputting the self-refresh frame to a display device of the display system; and adjusting the reading timing sequence signal according to the writing timing sequence signal and the reading timing sequence signal.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Chia-Hao Lee, Yu-Hsuan Huang, Chueh-An Tsai
  • Publication number: 20150318277
    Abstract: A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsiung-Shih CHANG, Jui-Chun CHANG, Shang-Hui TU, Priyono Tri Sulistyanto, Chia-Hao LEE
  • Patent number: 9130033
    Abstract: The invention provides a semiconductor device, including: a semiconductor device includes: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a trench formed in the substrate between the body and drift regions; a gate dielectric layer disposed adjacent to the trench; a liner lining the trench and adjoining with the gate dielectric layer; and a gate electrode formed over the gate dielectric layer and extending into the trench.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: September 8, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Priyono Tri Sulistyanto, Chia-Hao Lee, Rudy Octavius Sihombing, Shang-Hui Tu
  • Publication number: 20150206966
    Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Rahul KUMAR, Manoj KUMAR, Gene SHEU, Shao-Ming YANG, Rudy Octavius SIHOMBING, Chia-Hao LEE, Shang-Hui TU
  • Patent number: 9076862
    Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: July 7, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Priyono Tri Sulistyanto, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
  • Publication number: 20150155379
    Abstract: The invention provides a semiconductor device, including: a semiconductor device includes: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a trench formed in the substrate between the body and drift regions; a gate dielectric layer disposed adjacent to the trench; a liner lining the trench and adjoining with the gate dielectric layer; and a gate electrode formed over the gate dielectric layer and extending into the trench.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 4, 2015
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Manoj KUMAR, Priyono Tri SULISTYANTO, Chia-Hao LEE, Rudy Octavius SIHOMBING, Shang-Hui TU
  • Patent number: 9048115
    Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: June 2, 2015
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung Lee, Shang-Hui Tu, Gene Sheu, Neelam Agarwal, Karuna Nidhi, Chia-Hao Lee, Rudy Octavius Sihombing
  • Patent number: 9024281
    Abstract: An apparatus for implanting ions of a selected species into a semiconductor wafer includes an ion source, an accelerator, and an magnetic structure. The ion source is configured to generate an ion beam. The accelerator is configured to accelerate the ion beam, where the accelerated ion beam includes at least a first portion having a first energy and a second portion having a second energy. The magnetic structure is configured to deflect the first portion of the accelerated ion beam in a first path trajectory and the second portion of the accelerated ion beam in a second path trajectory. The first and second path trajectories have a same incident angle relative to a surface region of the semiconductor wafer.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 5, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Hanming Wu, Chia Hao Lee, John Chen
  • Publication number: 20140217501
    Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Priyono Tri SULISTYANTO, Rudy Octavius SIHOMBING, Chia-Hao LEE, Shang-Hui TU
  • Publication number: 20140117436
    Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung LEE, Shang-Hui TU, Gene SHEU, Neelam AGARWAL, Karuna NIDHI, Chia-Hao LEE, Rudy Octavius SIHOMBING
  • Publication number: 20140035029
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Inventors: Rudy Octavius Sihombing, Chia-Hao Lee, Tsung-Hsiung Lee, Shang-Hui Tu
  • Patent number: 8642427
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 4, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Rudy Octavius Sihombing, Chia-Hao Lee, Tsung-Hsiung Lee, Shang-Hui Tu