Patents by Inventor Chia-Hsin Hu
Chia-Hsin Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240151935Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.Type: ApplicationFiled: March 8, 2023Publication date: May 9, 2024Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
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Publication number: 20240151932Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.Type: ApplicationFiled: March 28, 2023Publication date: May 9, 2024Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
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Publication number: 20240152029Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.Type: ApplicationFiled: November 2, 2023Publication date: May 9, 2024Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
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Publication number: 20240151936Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.Type: ApplicationFiled: March 27, 2023Publication date: May 9, 2024Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
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Publication number: 20240155234Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.Type: ApplicationFiled: March 27, 2023Publication date: May 9, 2024Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
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Publication number: 20240128262Abstract: Bipolar junction transistor (BJT) structures are provided. First and second well regions are formed over a dielectric layer. A plurality of first and second gate-all-around (GAA) field-effect transistors are formed over a first well region. A plurality of third GAA field-effect transistors are formed over the second well region. Source/drain features of the first and third GAA field-effect transistors and the second well region have a first conductivity type. Source/drain features of the second GAA field-effect transistors and the first well region have a second conductivity type that is different from the first conductivity type. A first PN junction of a first BJT device is formed between the source/drain features of the first GAA field-effect transistors and the first well region, and a second PN junction of the first BJT device is formed between the first well region and the second well region.Type: ApplicationFiled: September 5, 2023Publication date: April 18, 2024Inventors: Shih-Chuan CHIU, Chia-Hsin HU, Zheng ZENG
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240038755Abstract: A semiconductor structure is provided. The semiconductor structure includes a logic cell. The logic cell includes a first transistor and a second transistor. The first transistor includes a first gate structure extending in a first direction and overlapping a first semiconductor fin. The second transistor includes a second gate structure extending in the first direction and overlapping the first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins extend in a second direction that is perpendicular to the first direction. The first and second transistors share a source/drain region, and one end of the first gate structure is formed between the first and second semiconductor fins.Type: ApplicationFiled: June 29, 2023Publication date: February 1, 2024Inventors: Chia-Hsin HU, Wei-Chieh TSENG, Zheng ZENG
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Publication number: 20240014295Abstract: Semiconductor structures of bipolar junction transistor (BJT) are provided. A first active region of a collection region is formed over a first P-type well region. Second and third active regions of a base region are formed over an N-type well region. A fourth active region of an emitter region is formed over a second P-type well region. The first active region includes a plurality of first fins and a plurality of first source/drain features epitaxially grown on the first fins. Each of the second and third active regions includes a plurality of second fins and a plurality of second source/drain features epitaxially grown on the second fins. The fourth active region includes a plurality of third fins and a plurality of third source/drain features epitaxially grown on the third fins. The second and third active regions are disposed on opposite sides of the fourth active region.Type: ApplicationFiled: June 1, 2023Publication date: January 11, 2024Inventors: Shih-Chuan CHIU, Chia-Hsin HU, Zheng ZENG
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Patent number: 11621351Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.Type: GrantFiled: May 3, 2021Date of Patent: April 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin Hu, Huan-Tsung Huang
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Publication number: 20220357211Abstract: The present invention provides a processing circuit including logic cells and a thermal sensor. The thermal sensor is positioned within the logic cells and surrounded by the logic cells, and the logic cells and the thermal sensor are all implemented by core devices.Type: ApplicationFiled: April 13, 2022Publication date: November 10, 2022Applicant: MEDIATEK INC.Inventors: Min-Hang Hsieh, Jyun-Jia Huang, Chien-Sheng Chao, Ghien-An Shih, Ching-Chung Ko, Yu-Cheng Su, Lin-Chien Chen, Ai-Yun Liu, Chia-Hsin Hu
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Patent number: 11244944Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.Type: GrantFiled: December 20, 2018Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Amit Kundu, Chia-Hsin Hu, Jaw-Juinn Horng
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Publication number: 20210257487Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.Type: ApplicationFiled: May 3, 2021Publication date: August 19, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin HU, Huan-Tsung HUANG
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Patent number: 10998443Abstract: The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions.Type: GrantFiled: April 15, 2016Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hsin Hu, Huan-Tsung Huang
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Publication number: 20210066193Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
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Patent number: 10840181Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: GrantFiled: December 21, 2018Date of Patent: November 17, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
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Patent number: 10340194Abstract: A method includes forming a gate stack over a semiconductor fin, wherein the semiconductor fin forms a ring, and etching a portion of the semiconductor fin not covered by the gate stack to form a recess. The method further includes performing an epitaxy to grow an epitaxy semiconductor region from the recess, forming a first contact plug overlying and electrically coupled to the epitaxy semiconductor region, and forming a second contact plug, wherein the second contact plug is overlying and electrically coupled to the gate stack.Type: GrantFiled: January 22, 2018Date of Patent: July 2, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hsin Hu, Min-Chang Liang
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Publication number: 20190148293Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: December 21, 2018Publication date: May 16, 2019Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
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Publication number: 20190131299Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.Type: ApplicationFiled: December 20, 2018Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Amit Kundu, Chia-Hsin Hu, Jaw-Juinn Horng
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Patent number: 10170414Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: GrantFiled: August 31, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen