Abstract: A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of the plurality of semiconductor fin, and a gate electrode over the gate dielectric. The device further includes a plurality of semiconductor regions, each disposed between and contacting two neighboring ones of the plurality of semiconductor fins. The device further includes a plurality of contact plugs, each overlying and electrically coupled to one of the plurality of semiconductor regions. An electrical connection electrically interconnects the plurality of semiconductor regions and the gate electrodes of the plurality of gate stacks.

Abstract: A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of the plurality of semiconductor fin, and a gate electrode over the gate dielectric. The device further includes a plurality of semiconductor regions, each disposed between and contacting two neighboring ones of the plurality of semiconductor fins. The device further includes a plurality of contact plugs, each overlying and electrically coupled to one of the plurality of semiconductor regions. An electrical connection electrically interconnects the plurality of semiconductor regions and the gate electrodes of the plurality of gate stacks.

Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.

Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.

Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.

Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.

Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.