Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.

Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.

Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer has two adhering surfaces having a same area and a middle cross section located at a middle position between the two adhering surfaces. An area of the middle cross section is 115% to 200% of an area of any one of the two adhering surfaces. The adhesive layer can provide for light to travel therethrough, and enables the light therein to change direction and to attenuate. The sensor chip, the adhesive layer, and the light-permeable layer are embedded in the encapsulant, and an outer surface of the light-permeable layer is at least partially exposed from the encapsulant.

Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.

Abstract: A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A method performed by a user equipment for a beam operation is provided. The method includes: receiving an RRC configuration for configuring a set of joint TCI states; receiving, from the BS, a MAC CE for activating a subset of joint TCI states in the set of joint TCI states, the MAC CE is used to map the subset of joint TCI states to codepoints of a TCI field in DCI; receiving the DCI indicating a joint TCI state included in the subset of joint TCI states activated by the MAC CE; determining whether the DCI includes a DL assignment; transmitting, in response to reception of the DCI, first HARQ-ACK information in a case that the DCI does not include the DL assignment; and transmitting, in response to the reception of the DCI and reception of a PDSCH, second HARQ-ACK information in a case that the DCI includes the DL assignment.

Abstract: A wireless communication method and apparatus for handling radio resource collision are provided. The wireless communication method includes receiving a Radio Resource Control (RRC) configuration indicating a first Control Resource Set (CORESET) pool index associated with a Physical Uplink Control Channel (PUCCH) designated to carry Uplink Control Information (UCI); determining whether the PUCCH overlaps one or more Physical Uplink Shared Channels (PUSCHs) in time domain; after determining that the PUCCH overlaps at least one of the one or more PUSCHs in the time domain, multiplexing the UCI on a particular PUSCH of the one or more PUSCHs that is associated with the first CORESET pool index; and transmitting the UCI via the particular PUSCH.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.