Patents by Inventor Chia-Hung Lin

Chia-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096998
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
  • Patent number: 11935836
    Abstract: A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, An-Jhih Su, Der-Chyang Yeh, Shih-Guo Shen, Chia-Nan Yuan, Ming-Shih Yeh
  • Publication number: 20240089943
    Abstract: A method performed by a user equipment for a beam operation is provided. The method includes: receiving an RRC configuration for configuring a set of joint TCI states; receiving, from the BS, a MAC CE for activating a subset of joint TCI states in the set of joint TCI states, the MAC CE is used to map the subset of joint TCI states to codepoints of a TCI field in DCI; receiving the DCI indicating a joint TCI state included in the subset of joint TCI states activated by the MAC CE; determining whether the DCI includes a DL assignment; transmitting, in response to reception of the DCI, first HARQ-ACK information in a case that the DCI does not include the DL assignment; and transmitting, in response to the reception of the DCI and reception of a PDSCH, second HARQ-ACK information in a case that the DCI includes the DL assignment.
    Type: Application
    Filed: January 12, 2022
    Publication date: March 14, 2024
    Applicant: FG Innovation Company Limited
    Inventors: CHIA-HAO YU, JIA-HONG LIOU, CHIA-HUNG LIN
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240089062
    Abstract: A wireless communication method and apparatus for handling radio resource collision are provided. The wireless communication method includes receiving a Radio Resource Control (RRC) configuration indicating a first Control Resource Set (CORESET) pool index associated with a Physical Uplink Control Channel (PUCCH) designated to carry Uplink Control Information (UCI); determining whether the PUCCH overlaps one or more Physical Uplink Shared Channels (PUSCHs) in time domain; after determining that the PUCCH overlaps at least one of the one or more PUSCHs in the time domain, multiplexing the UCI on a particular PUSCH of the one or more PUSCHs that is associated with the first CORESET pool index; and transmitting the UCI via the particular PUSCH.
    Type: Application
    Filed: March 31, 2022
    Publication date: March 14, 2024
    Inventors: WAN-CHEN LIN, CHIA-HAO YU, CHIA-HUNG LIN, HAI-HAN WANG
  • Patent number: 11929327
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Inc.
    Inventors: Hsu-Kai Chang, Keng-Chu Lin, Sung-Li Wang, Shuen-Shin Liang, Chia-Hung Chu
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240079483
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.
    Type: Application
    Filed: March 22, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hung LIN, I-Hsieh WONG, Tzu-Hua CHIU, Cheng-Yi PENG, Chia-Pin LIN
  • Publication number: 20240075291
    Abstract: A close-loop deep brain stimulation algorithm system for Parkinson's disease includes a memory and a processor. The processor includes a deep brain stimulation (DBS) simulation module, a virtual brain network module, a feature extraction module, and a reinforcement learning module. The deep brain stimulation simulation module is adapted to combine a deep brain stimulation waveform according to the stimulation frequency and the stimulation amplitude and output the deep brain stimulation waveform. The virtual brain network module is adapted to receive the deep brain stimulation waveform to output a synaptic signal and calculate a reward parameter. The feature extraction module is adapted to receive the synaptic signal and extract a plurality of feature values according to the synaptic signal.
    Type: Application
    Filed: December 27, 2022
    Publication date: March 7, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chii-Wann Lin, Chia-Hung Cho
  • Patent number: 11916314
    Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: February 27, 2024
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Patent number: 11916273
    Abstract: A rotary joint includes a shaft having a first end, a second end, and a cavity. The rotary joint includes a first waveguide section having a first proximal end and a first distal end. The first proximal end of the first waveguide section is positioned within the cavity and secured to the inner surface of the shaft. The rotary joint includes a second waveguide section that includes a second proximal end and a second distal end. The second proximal end of the second waveguide section is positioned within the cavity of the shaft and unsecured to the inner surface of the shaft to form a radial gap between an outer surface of the second proximal end and a laterally adjacent portion of the inner surface of the shaft. The shaft and the first waveguide section are configured to rotate about the rotational axis and relative to the second waveguide section.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: February 27, 2024
    Assignee: Waymo LLC
    Inventors: Zhe Li, Samuel Lenius, Chia-Hung Lin, Craig Moriwaki, William Martin Peters, Jr., Kelvin Kwong, Robert J. Lockwood, Peng Ye
  • Publication number: 20240057111
    Abstract: A method for a unified Transmission Configuration Indication (TCI) state operation performed by a user equipment (UE) is provided. The method includes receiving a first Radio Resource Control (RRC) configuration for configuring a first set of TCI states and a second set of TCI states; receiving a first indication for associating the first set of TCI states with a first channel, the first channel including a Physical Downlink Control Channel (PDCCH); receiving a second indication for associating the second set of TCI states with a second channel, the second channel being scheduled by first Downlink Control Information (DCI) received on the first channel; receiving a third indication for indicating at least one third TCI state to be applied on the second channel; and transmitting or receiving the second channel after applying the at least one third TCI state.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 15, 2024
    Inventors: WAN-CHEN LIN, CHIA-HUNG LIN, MEI-JU SHIH
  • Publication number: 20240041166
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Patent number: 11895927
    Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: February 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
  • Patent number: 11895043
    Abstract: The present invention provides a method for accessing a system memory, wherein the method includes the steps of: reading a descriptor from the system memory, where the descriptor includes a buffer start address field and a buffer size field, wherein the buffer start address field includes a start address of a buffer in the system memory, and the buffer size field indicates a size of the buffer; receiving multiple packets, and writing the multiple packets in to the buffer; modifying the descriptor according to the multiple packets stored in the buffer to generate a modified descriptor, wherein the modified descriptor only comprises information of part of the multiple packets or does not comprise information of any one of the multiple packets; and writing the modified descriptor into the system memory.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: February 6, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Hung Lin
  • Publication number: 20240020998
    Abstract: A character recognition method includes the stages as detailed in the following paragraph. An image is received, wherein the image is one in a plurality of consecutive images. A target object in the image is detected. Object information of the target object is defined according to the area ratio of the target object occupied in the image. Whether the target object in the image is the same as the target object in the previous image is determined according to the object information. Character recognition on the target object is performed to obtain a recognition result. The weighting score of the recognition result is calculated according to the object information and the recognition result. The weighting score of the recognition result of the target object in the consecutive images is accumulated until the weighting score is higher than a preset value, and the recognition result is output.
    Type: Application
    Filed: October 12, 2022
    Publication date: January 18, 2024
    Inventors: Chen-Chung LEE, Chia-Hung LIN, Chun-Hung CHEN, Chien-Kuo HUNG, Wen-Kuang CHEN, En-Chi LEE
  • Publication number: 20230397696
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 14, 2023
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Patent number: 11841218
    Abstract: Herein disclosed are a surface topography measuring system and a method thereof. The method comprises the following steps: dividing a test beam into a first sub-beam, entering a reflecting mirror along a first axis, and a second sub-beam, entering an object surface along a second axis; moving the reflecting mirror for reflecting the first sub-beam at different positions on the first axis to generate N reflected beams; generating an object reflected beam, related to the second sub-beam, reflected from the object surface; generating N images, related to the N reflected beams and the object reflected beam, and each of the N images having a plurality of interference fringes; analyzing the interference fringes in each of the N images to calculate N curve formulas; calculating a surface topography of the object surface from the N curve formulas.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: December 12, 2023
    Assignee: Chroma ATE Inc.
    Inventors: Shih-Yao Pan, Chih-Yao Ting, Chia-Hung Lin, Hsin-Yun Chang
  • Patent number: 11825915
    Abstract: An apparatus for buffing a shoe part includes a housing adapted to be articulated around at least a portion of the footwear part. A rotating spindle is positioned in the housing and has a buffing surface for engagement with the footwear part. A carriage is slideably connected to the housing and holds the spindle such that the buffing surface can be moved closer to and further away from the footwear part. An actuator is in the housing and in contact with the carriage. The actuator applies force to the carriage to increase the force of the buffing surface onto the footwear part. A biasing member is in the housing and in contact with the carriage. The biasing member exerts force onto the carriage in a direction opposite the force exerted by the actuator.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: November 28, 2023
    Assignee: NIKE, Inc.
    Inventors: Dragan Jurkovic, Shih-Yuan Wu, Chia-Wei Chang, Wen-Ruei Chang, Chien-Chun Chen, Chang-Chu Liao, Chia-Hung Lin
  • Patent number: 11825916
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 28, 2023
    Assignee: NIKE, Inc.
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu