Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, a gate connected to the first node, and has a gate connected to the first node. Sources of the first and second PMOS transistors share a P+ doped region in N-type well region, and the first PMOS transistor is disposed between the second PMOS transistor and the first and second NMOS transistors.

Abstract: A front end module includes a first radio frequency (RF) terminal, a second RF terminal, a third RF terminal, a transmission path and a reception path. The transmission path is formed between the first RF terminal and the third RF terminal. The reception path is formed between the first RF terminal and the second RF terminal. The reception path includes a first set of switches, a second set of switches, a third set of switches and an amplifier. An amplifier is coupled to the second set of switches and the second RF terminal. The third set of switches is coupled to the first set of switches and the second RF terminal. When a transmission signal is transmitted to the first RF terminal via the transmission path, the first set of switches, the second set of switches and the third set of switches are turned off.

Abstract: A method for multi-spectral scattering-matrix tomography includes a step of splitting an input light signal into an incident light signal and a reference light signal. The sample light signal is directed to a sample in either a reflection configuration or a transmission configuration such that an output light signal includes light scattered from or transmitted through the sample. The incident signal and the reference light signal are directed to a camera angled to allow for amplitude and phase to be calculated by off-axis holography. A total light signal is measured with a camera that is a coherent sum of the reference light signal and the output signal. The total light signal for each light frequency and each incident angle are collected as collected total light signal data. A computing device derives an image of the sample from a calculated reflection matrix or transmission matrix or both of them.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on a channel region of a semiconductor feature; depositing a work function tuning layer on the gate dielectric layer, the work function tuning layer including a first work function tuning element; depositing a capping layer on the work function tuning layer with atomic layer deposition, the capping layer formed of an oxide or a nitride; performing an anneal process while the capping layer covers the work function tuning layer, the anneal process driving the first work function tuning element from the work function tuning layer into the gate dielectric layer; removing the capping layer to expose the work function tuning layer; and depositing a fill layer on the work function tuning layer.

Abstract: A lens system having reduced physical size. The lens system includes multiple metalenses, lenses with metasurfaces, that integrate the lens and the free space and compress them into multiple layers of metasurfaces, significantly reducing the overall volume and weight of the imaging system while increasing its efficiency. The lens system also provides for tools that can accurately model 3D multilayer metasurfaces, carry out inverse design to find the optimal and fault-tolerant structure, fabricate the metasurfaces with multi-project wafer service, assemble them with a 3D-printed holder, and characterize the performance of the resulting ultra-compact imaging system.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor substrate having a first protected circuit, and forming a first guard ring around the first protected circuit including: forming a first wall configured to provide a first reference voltage; and forming a second wall configured to provide a second reference voltage different than the first reference voltage.

Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.

Abstract: Certain embodiments are directed to compositions and methods for solving problems associated with measuring T:G mispairs, U:G mispairs and other 5-substituted uracil mispairs. Certain embodiments are directed to a hybrid enzyme that is capable of finding and cutting the T of the T:G mispair or other mispaired uracil analogs creating a method for their measurement. In certain embodiments the hybrid enzyme is a fusion of a human thymine DNA glycosylase (TDG) activator segment and a catalytic domain of an archaeal thermophilic thymine glycosylase (tTDG).

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A detection device includes a cover, a detection module, and a light source. The cover includes a top wall and a sidewall connected to the top wall. The top wall and the sidewall cooperatively define a receiving cavity. The sidewall includes a first portion close to the top wall and a second portion away from the top wall. The detection module is disposed on the top wall. The light source is disposed on the second portion. The influence of heat on proper operation of the detection device is prevented.

Abstract: A detection device includes a substrate, a light source, a detection module, and a heat dissipation module. The substrate includes a first base plate, a second base plate, and at least one connecting portion connecting the first base plate to the second base plate. The light source is disposed on the first base plate. The detection module is disposed on the second base plate. The first base plate has a first surface towards the at least one connecting portion, and the at least one connecting portion has a second surface towards the first base plate. The second surface is connected to a portion of the first surface. The heat dissipation module is disposed on the at least one connecting portion and/or the second base plate, and the influence of heat on proper operation of the detection device is thus prevented.

Abstract: The present disclosure provides electronic device and control method thereof. The electronic device includes input circuit and processor. The input circuit includes key switches arranged in array. The processor is coupled to the key switches through column lines and row lines and is configured to: detect part of the row lines and part of the column lines coupled to at least one turned-on key switch; assign one of the part of the row lines and the part of the column lines as scan line group, and assign the other of the part of the row lines and the part of the column lines as return line group; input corresponding scan signal to corresponding scan line of the scan line group; and detect whether the return line group outputs the corresponding scan signal, to confirm position of the at least one turned-on key switch.

Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.

Abstract: The mask data corresponding to each data element of the issued instruction may be handled by a mask queue, where only the valid mask data are stored to the mask queue. The mask data of multiple vector instructions may be stored in the mask queue. The corresponding mask data may be accessed from the mask queue when the vector instruction(s) is dispatched from the execution queue to the functional unit for execution. In the case of 512-bit wide mask data is needed, the issuing of the vector instruction from the decode/issue unit to the execution queue may be stalled until the mask queue is available. In some embodiments, one mask queue may be dedicated to one execution queue. Alternatively, one mask queue may be shared between two different execution queues. In the disclosure, resources are conserved without dedicating additional storage space for handling mask data of the vector instruction.

Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.