Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material over an underlying layer. The spacer material has sidewalls defining a first trench. A cut material is formed over the spacer material and within the first trench. The cut material separates the trench into a pair of trench segments having ends separated by the cut material. The underlying layer is patterned according to the spacer material and the cut material.

Abstract: A method, system and computer program product for self-learned and probabilistic-based prediction of inter-camera object movement is disclosed. The method includes building and storing a transition model defined by transition probability and transition time distribution data generated during operation of a first video camera and one or more other video cameras over time. The method also includes employing at least one balance flow algorithm on the transition probability and transition time distribution data to determine a subset of the video cameras to initiate a search for an object based on a query. The method also includes running the search for the object over the subset of the video cameras.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a hard mask over a dielectric layer of a substrate. A blocking layer is formed on the hard mask and spacers are formed over the blocking layer. The spacers laterally straddle opposing edges of the blocking layer. The hard mask is etched according to the spacers and the blocking layer. The dielectric layer is etched according to the hard mask.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: The disclosure provides seals for devices that operate at elevated temperatures and have reactive metal vapors, such as lithium, sodium or magnesium. In some examples, such devices include energy storage devices that may be used within an electrical power grid or as part of a standalone system. The energy storage devices may be charged from an electricity production source for later discharge, such as when there is a demand for electrical energy consumption.

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Abstract: A method for predicting immunotherapy response of a subject having cancer includes the following steps. A peripheral blood sample is obtained from the subject having cancer before or after receiving the immunotherapy. The number of immune cells in the peripheral blood sample of the subject having cancer is detected. The number of immune cells and a first cut-off value/or a second cut-off value are compared to indicate whether the subject having cancer benefits from the immunotherapy. The first cut-off value/or the second cut-off value is determined by the following steps: a statistical analysis of a correlation between the number of immune cells in a group of subjects having cancer and an expected risk of disease progression in the group of subjects having cancer is performed, and then a statistically significant value used to define the correlation is obtained.

Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.

Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.

Abstract: In some embodiments, the disclosure relates to an integrated circuit structure. The integrated circuit structure has a substrate and a first hard mask layer over the substrate. An island of a second hard mask layer is arranged on the first hard mask layer and is set back from sidewalls of the first hard mask layer. A sacrificial mask is disposed over the island of the second hard mask layer. The sacrificial mask has sidewalls that define an opening exposing upper surfaces of the first hard mask layer and the island of the second hard mask layer. The island of the second hard mask layer extends from below the sacrificial mask to laterally past the sidewalls of the sacrificial mask.

Abstract: The disclosure provides seals for devices that operate at elevated temperatures and have reactive metal vapors, such as lithium, sodium or magnesium. In some examples, such devices include energy storage devices that may be used within an electrical power grid or as part of a standalone system. The energy storage devices may be charged from an electricity production source for later discharge, such as when there is a demand for electrical energy consumption.

Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material over an underlying layer. The spacer material has sidewalls defining a first trench. A cut material is formed over the spacer material and within the first trench. The cut material separates the trench into a pair of trench segments having ends separated by the cut material. The underlying layer is patterned according to the spacer material and the cut material.

Abstract: Methods, systems, and techniques for object detection and tracking are provided. A system may include a module configured to generate a plurality of region proposals, each region proposal comprising a part of a video frame, a CNN pre-trained for object detection, the plurality of region proposals being input to the CNN; a tracker for tracking one or more targets based on outputs from the CNN across the series of video frames and generating tracking information on the one or more targets; and a module further configured to refine the plurality of region proposals to be input to the CNN, based on the tracking information.

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.