Abstract: A method for manufacturing an elastic fiber and the elastic fiber are provided. The method includes: providing a thermoplastic polyester elastomer; drying the thermoplastic polyester elastomer; melting the thermoplastic polyester elastomer by an extruder to form a melt; extruding the melt by a spinneret plate to form a plurality of filamentous streams; feeding the filamentous streams into a spinning channel for cooling and curing to form a plurality of monofilaments; and bundling and oiling the monofilaments by an oil wheel, after extending and guiding the monofilaments by a first godet roller and a second godet roller, and winding the monofilaments by a winder to obtain a thermoplastic polyester elastic fiber.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.

Abstract: A display device includes a display module and a camera module. The camera module includes a first housing, a second housing and a camera unit. The first housing is movably disposed on the display module. The second housing is separably connected to the first housing. The camera unit is disposed on the second housing. The second housing is able to move with the first housing in relative to the display module, such that the camera unit is exposed from the display module or hidden in the display module. When the second housing is separated from the first housing, the second housing is able to rotate in relative to the first housing, so as to adjust an orientation of the camera unit.

Abstract: An aluminum plastic film for a lithium battery and a method for manufacturing the same are provided. The method includes steps as follows: preparing a polyolefin adhesive; coating the polyolefin adhesive onto one surface of an aluminum foil layer; disposing an inner polyolefin layer onto the polyolefin adhesive; and drying the polyolefin adhesive, so that a polyolefin adhesive layer is formed between the aluminum foil layer and the inner polyolefin layer. Components of the polyolefin adhesive include a modified polyolefin polymer and a hardener. The modified polyolefin polymer has a modified group, a structure of the modified group contains maleic anhydride, and a molecular weight of the modified polyolefin polymer ranges from 100,000 g/mol to 200,000 g/mol.

Abstract: A case tampering detection device, used for a computer system covered with a computer case, includes at least one detector for detecting whether the computer case is opened and generating a detection result; a storage unit; a microcontroller unit, coupled to the storage unit, for generating a case tampering event and storing the case tampering event in the microcontroller unit or the storage unit when being powered; and a power supply unit, coupled to the at least one detector, for receiving the detection result, and supplying power to the microcontroller unit when the detection result indicates that the computer case is opened.

Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: A method for determining a standard depth value of a marker includes obtaining a maximum depth value of the marker. A reference depth value of the marker is obtained based on a depth image of the marker, and a Z-axis coordinate value of the marker is obtained based on a color image of the marker. When the reference depth value and the Z-axis coordinate value are both less than the maximum depth value, and a difference between the reference depth value and the Z-axis coordinate value is not greater than 0, the depth reference value is set as the standard depth value of the marker; and when the difference is greater than 0, the Z-axis coordinate value is set as the standard depth value of the marker.

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: A photomask structure having a first region and a second region is provided. The layout pattern density of the first region is smaller than the layout pattern density of the second region. The photomask structure includes a first layout pattern, a second layout pattern, and first assist patterns. The first layout pattern is located in the first region and the second region. The second layout pattern is located in the second region. The second layout pattern is located on one side of the first layout pattern. The first assist patterns are located on the first sidewall of the first layout pattern and separated from each other. The first sidewall is adjacent to the second layout pattern. The first assist patterns are adjacent to a boundary between the first region and the second region. The lengths of two adjacent first assist patterns decrease in the direction away from the boundary.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.