Abstract: A chip packaging structure and a chip packaging method are provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate, and the image sensing chip has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The supporting member is formed by stacking microstructures with each other, so that the supporting member has pores. The second substrate is disposed on an upper surface of the supporting member, and the second substrate, the supporting member, and the image sensing chip define an air cavity. The encapsulant is attached to the upper surface of the first substrate and a side surface of the second substrate and filled into the pores.

Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.

Abstract: A liquid cooling head includes a bottom plate, a heat dissipation plate, a partition plate and an upper cover plate. The bottom plate includes an opening, and the heat dissipation plate, the partition plate and the upper cover plate are fixed to the bottom plate. The partition plate divides the opening into a plurality of cooling chambers, and each cooling chamber is equipped with a cooling liquid inlet, a cooling liquid outlet, a pump and an electric control device. The cooling liquid inlet and the cooling liquid outlet are formed in the upper cover plate, the pump is fluid-connected to the cooling liquid outlet, and the electric control device drives the pump to rotate, so that the cooling liquid flows through the cooling chamber to cool one heat source below the heat dissipation plate. In addition, a liquid cooling device with the liquid cooling head is also disclosed therein.

Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.

Abstract: Provided is a composition including a lactic acid bacterium and a carrier thereof for prophylaxis or treatment of an allergy. The lactic acid bacterium is Lactobacillus paragasseri, such as Lactobacillus paragasseri BBM171 deposited under DSMZ Accession No. DSM 34311. Also provided is a method for preventing or treating an allergy in a subject that includes administering an effective amount of the composition of Lactobacillus paragasseri to the subject.

Abstract: Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.

Abstract: A virtual reality tracker includes a first part and a second part. The first part includes a plurality of first light-emitting diodes (LEDs) and an inner measurement unit (IMU). The inertial measurement unit is used for measuring the acceleration and the triaxial angular velocity of the first part. The second part includes a plurality of second light-emitting diodes. Moreover, the first part and the second part are connected by a flexible component.

Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A sensor package structure is provided and includes a substrate, a sensor chip mounted on the substrate, a supporting layer being ring-shaped and disposed on the sensor chip, a light-permeable layer, and a grooved shielding layer that is ring-shaped and that is disposed on a lower surface of the light-permeable layer. The grooved shielding layer includes an inner barrier and an outer barrier respectively located at two opposite sides of the supporting layer. An inner edge of the inner barrier has an opening directly located above a sensing region of the sensor chip. The inner barrier, the outer barrier, and a part of the lower surface of the light-permeable layer jointly define a ring-shaped groove. The part of the lower surface of the light-permeable layer is disposed on the supporting layer, so that a part of the supporting layer is arranged in the ring-shaped groove.

Abstract: Present invention is related to a polyimide of formula as following: and a ketone-containing alicyclic dianhydride of formula as following: wherein: R1, R2, R3, R4 denote hydrogen atom or carbon containing functional group with carbon number at a range of 1-4; R5 denotes diamine group; and n equals to any positive integer.

Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first microelectronic elements on a first temporary substrate; and replacing at least one defective microelectronic element of the first microelectronic elements with at least one second microelectronic element. The first microelectronic elements and at least one second microelectronic element are distributed on the first temporary substrate. The first microelectronic elements and at least one second microelectronic element have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first microelectronic elements and at least one second microelectronic element. A semiconductor structure and a display panel are also provided.

Abstract: A cell culture device includes a culture unit, a gas supply unit, a first pressure unit, at least one inspecting unit and a control unit. The culture unit contains a cell culture liquid. The gas supply unit, connected with the culture unit, is used for transmitting a culture gas into the culture unit. The first pressure unit, connected with the culture unit, is used for applying a pressure to the cell culture liquid in the culture unit. The at least one inspecting unit, connected with the culture unit, is used for receiving the cell culture liquid for inspection. The control unit, electrically coupled with the culture unit, the first pressure unit, the gas supply unit and the at least one inspecting unit, is used for monitoring corresponding condition parameters to determine respective operations. In addition, a cell culture method for the cell culture device is also provided.

Abstract: A package structure includes a first substrate and a first device disposed on the first substrate. The first device includes at least one anchor structure, a film structure anchored by the anchor structure and an actuator configured to control the film structure to form a first vent temporarily. The film structure partitions a space into a first volume to be connected to an ear canal and a second volume connected to an ambient of a wearable sound device. The ear canal and the ambient are connected via the first vent when the first vent is opened. The first vent is opened by controlling a first membrane portion and a second membrane portion of the film structure, such that a difference between a first displacement of the first membrane portion and a second displacement of the second membrane portion is larger than a thickness of the film structure.

Abstract: A sound producing cell includes a membrane and an actuating layer. The membrane includes a first membrane subpart and a second membrane subpart, wherein the first membrane subpart and the second membrane subpart are opposite to each other. The actuating layer is disposed on the first membrane subpart and the second membrane subpart. The first membrane subpart includes a first anchored edge which is fully or partially anchored, and edges of the first membrane subpart other than the first anchored edge are non-anchored. The second membrane subpart includes a second anchored edge which is fully or partially anchored, and edges of the second membrane subpart other than the second anchored edge are non-anchored.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: A package structure includes a cover and a cell disposed within the cover. The cell includes a membrane, an actuating layer and an anchor structure. The membrane includes a first membrane subpart and a second membrane subpart, wherein the first membrane subpart and the second membrane subpart are opposite to each other in a top view. The actuating layer is disposed on the first membrane subpart and the second membrane subpart in the top-view direction. The membrane is anchored by the anchor structure. The first membrane subpart includes a first anchored edge which is fully or partially anchored, and edges of the first membrane subpart other than the first anchored edge are non-anchored. The second membrane subpart includes a second anchored edge which is fully or partially anchored, and edges of the second membrane subpart other than the second anchored edge are non-anchored.

Abstract: A supporter is provided. The supporter includes a base, a holder, a positioning member, a connecting rod assembly, and a power assembly. The holder is connected to the base and has a through-hole. The positioning member is disposed in the through-hole of the holder. The connecting rod assembly is disposed on the holder and connected to the positioning member. The power assembly is movably disposed on the holder via the connecting rod assembly. Accordingly, the power assembly is movable in response to the position of the electronic device, which achieves good recharge efficiency whether the electronic device is arranged upright or horizontally.

Abstract: A package substrate and a method for fabricating a chip assembly are provided. The method includes: providing a substrate, which has an upper substrate surface and a lower substrate surface, the upper substrate surface is divided into a plurality of scribe line regions that define a plurality of die-bonding regions, and any adjacent two of the die-bonding regions are separated by the scribe line regions. The die-bonding region is provided with a substrate conductor and a core material body, the substrate conductor penetrates the substrate and has upper and lower conductive ends exposed on the upper and lower substrate surfaces, respectively, and the core material body is disposed adjacent to the substrate conductor in the substrate. The method further includes: fixing chips in the die-bonding regions, respectively; and performing a dicing process along a plurality of scribe lines defined by the scribe line regions to form chip assemblies.

Abstract: The invention relates to a heat management structure with graphene and copper, and a formation method thereof, comprising a copper foil layer provided, then forming a graphene layer on the copper foil layer surface, and forming an electroplating copper layer on the graphene layer surface, and eventually forming an electroplating copper layer-graphene layer-copper foil layer sandwich heat management structure.