Patents by Inventor Chien-Chung Huang

Chien-Chung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770345
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chang-Sheng Lin, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh
  • Publication number: 20200266340
    Abstract: An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Publication number: 20200253403
    Abstract: A biodegradable drinking straw and a manufacturing method thereof, the biodegradable drinking straw includes: a plant fiber material, which accounts for 5 wt % to 60 wt % of the total weight of the biodegradable drinking straw; and a biodegradable plastic selected from polylactic acid (PLA), polybutylene succinate (PBS) or a combination thereof; the biodegradable plastic accounts for 40 wt % to 95 wt % of the total weight of the biodegradable drinking straw; the fiber material is mixed into the biodegradable plastic and mixed uniformly and then extruded to form a tube body of the biodegradable drinking straw by extrusion molding. By replacing the traditional straw material with plant fibers and biodegradable plastics, the biodegradable drinking straw can be quickly decomposed naturally in the environment after being buried, thus reducing environmental pollution, and meeting the environmental protection requirements.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventor: CHIEN-CHUNG HUANG
  • Patent number: 10651373
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
  • Publication number: 20200136026
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20200106008
    Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 2, 2020
    Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
  • Publication number: 20200106007
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.
    Type: Application
    Filed: November 16, 2018
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Publication number: 20200066698
    Abstract: A light-emitting module and a tandem light-emitting device include an insulating housing, a control chip, a light-emitting unit, and a plurality of pins. The insulating housing has an upper accommodating space and a lower accommodating space, the lower accommodating space is below the upper accommodating space directly, and the upper accommodating space forms an opening at the upper end of the insulating housing. The control chip is located in the lower accommodating space. The light-emitting unit is located in the upper accommodating space and is electrically connected to the control chip. A plurality of pins are exposed outside the insulating housing. The control chip can receive an electrical signal transmitted by an external control device through the pins to control the illumination of the light-emitting unit.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 27, 2020
    Inventors: CHIEN-CHUNG HUANG, HSIN-NU LI, JUN-JIE HE
  • Publication number: 20200066580
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: Tai-Yen PENG, Chang-Sheng LIN, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH
  • Publication number: 20200035907
    Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.
    Type: Application
    Filed: January 8, 2019
    Publication date: January 30, 2020
    Inventors: TAI-YEN PENG, YU-SHU CHEN, CHIEN CHUNG HUANG, SIN-YI YANG, CHEN-JUNG WANG, HAN-TING LIN, JYU-HORNG SHIEH, QIANG FU
  • Publication number: 20200015612
    Abstract: A biodegradable drinking straw is made of plant fiber powder and at least one polymer. The at least one polymer is polylactide (PLA), polybutylene succinate (PBS), or polypropylene (PP). As an alternative of drinking straws made of traditional plastic materials, the biodegradable drinking straw when buried in landfills can be degraded by microorganisms and decay, eventually becoming a part of the nature again. Besides, the biodegradable drinking straw is made of neither non-petrochemical materials nor silica, so its production avoids excessively consuming the finite resources, thereby being contributive to energy conservation and environmental protection.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Inventor: CHIEN-CHUNG HUANG
  • Publication number: 20200000176
    Abstract: A method for manufacturing a shoe part includes: the first mixing step, the standing step, the second mixing step, the setting step, and the hot press forming step. The invention mainly uses the waste coffee grounds material as raw material to manufacture the shoe part. In addition to the aroma of coffee, the shoes have the functions of deodorization and dehumidification while being worn by the user, thereby achieving multiple objectives of environmentally friendly materials, low cost, strong structure and environmentally friendly after-use treatment.
    Type: Application
    Filed: January 22, 2019
    Publication date: January 2, 2020
    Inventors: SHU-LI CHANG, CHIEN-CHUNG HUANG, YENG-FONG SHIH
  • Publication number: 20190380433
    Abstract: The present invention provides a shoe material part mainly composed of a coffee ground material, a porous material and a rubber-plastic material, and is made of a recycled waste porous material and recycled waste coffee grounds, which can improve the value of waste recycling and reuse, and reduce environmental pollution, in addition to reducing waste, there will be no residue pollution of natural ecology and other issues in the subsequent environmental recycling, quite in line with environmental requirements. In addition, the present invention has the function of natural deodorization, because the coffee grounds can naturally diffuse the aroma of coffee, and the characteristics of better deodorization and air permeability of the coffee grounds can be used to reduce the foul smell of a user's foot.
    Type: Application
    Filed: January 22, 2019
    Publication date: December 19, 2019
    Inventors: SHU-LI CHANG, CHIEN-CHUNG HUANG, YENG-FONG SHIH
  • Patent number: 10510867
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20190140076
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 10157997
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20180315830
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 1, 2018
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 10025155
    Abstract: The present disclosure provides a bottom electrode substrate for a segment-type electrophoretic display. The bottom electrode substrate includes a flexible substrate, a first conductive layer, an insulating layer, a second conductive layer and a segment-type electrode. The first conductive layer is disposed on the flexible substrate. The insulating layer covers the first conductive layer and the flexible substrate, wherein the insulating layer has at least one opening exposing a part of the first conductive layer. The second conductive layer is filled in the opening and in contact with the exposed first conductive layer. The segment-type electrode covers the second conductive layer and the insulating layer, and is in contact with the second conductive layer. A method for manufacturing the bottom electrode substrate is also provided herein.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: July 17, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Huai-Tze Yang, Wei-Juin Chen, Chien-Chung Huang
  • Patent number: 9721840
    Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: August 1, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Chien-Chung Huang, Yu-Ting Tseng, Ya-Huei Tsai, Yu-Ping Wang
  • Patent number: 9697909
    Abstract: A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal. The second switch selectively forces a voltage level of the first output signal to be equal to a voltage level of a second clock signal based on both of the second clock signal and a third clock signal inverted to the second clock signal. The third switch selectively defines a voltage over the control terminal to be a first voltage based on a first input signal. The fourth switch selectively forces the voltage level over the control terminal to be equal to the voltage level of the second clock signal based on both of the second clock signal and the third clock signal.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: July 4, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Ya-Ling Chen, Ching-Kai Lo, Chien-Chung Huang, Hua-Gang Chang