Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Abstract: A mobile display system includes a first mobile display device and a second mobile display device. The first mobile display device includes a first power storage module, a first screen, and a wireless power transmitter. The first screen is configured to display a first image by using the power stored in the first power storage module. The second mobile display device includes a second power storage module, a second screen, and a wireless power receiver. The second screen is configured to display a second image by using the power stored in the second power storage module. During a period when the first power storage module is charged, the wireless power transmitter provides a first wireless power signal to the wireless power receiver, so as to charge the second power storage module by the first wireless power signal.

Abstract: A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer.

Abstract: A multichip package structure for generating a symmetrical and uniform light-blending source includes a substrate unit, a light-emitting unit and a package unit. The substrate unit includes a substrate body and at least one bridging conductive layer disposed on the top surface of the substrate body. The light-emitting unit includes at least two first light-emitting elements diagonally disposed on the substrate body and electrically connected to the substrate body and at least two second light-emitting elements diagonally disposed on the substrate body and electrically connected to the substrate body. The package unit includes at least two first light-transmitting package bodies respectively covering the at least two first light-emitting elements and at least two second light-transmitting package bodies respectively covering the at least two second light-emitting elements.

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

Abstract: An LED base module includes a substrate and several driving units disposed on the substrate. Each driving unit includes a circuit layer, a separating wall, an LED driving component, a packaging member, and two electrodes. The circuit layer, the separating wall, and the electrodes are disposed on the substrate. A portion of the substrate corresponding to each driving unit is provided with an LED area and an electronic component area defined by the separating wall. The LED driving component is disposed on a portion of the circuit layer arranged in the electronic component area. The packaging member is formed on the electronic component area to entirely cover the LED driving component. A portion of the circuit layer arranged in the LED bonding area is used to bond to an LED chip, and the separating wall is configured to separate the LED chip and the LED driving component.

Abstract: An LED package structure for preventing lateral light leakage includes a substrate unit, a light-emitting unit, a light-transmitting unit and a light-shielding unit. The substrate unit includes a circuit substrate. The light-emitting unit includes at least one LED chip disposed on the circuit substrate and electrically connected to the circuit substrate. The light-transmitting unit includes a light-transmitting gel body disposed on the circuit substrate for enclosing the LED chip. The light-transmitting gel body has a first light-transmitting portion disposed on the circuit substrate for enclosing the LED chip and at least one second light-transmitting portion projected upwardly from the first light-transmitting portion and corresponding to the LED chip, and the second light-transmitting portion has a light output surface. The light-shielding unit includes a light-shielding gel body disposed on the circuit substrate for exposing the light output surface of the second light-transmitting portion.

Abstract: A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: An LED lighting device includes a circuit board, an LED die module, an LED driving component, and a translucent packaged body. The circuit board has a thermally conductive substrate, an electrically conductive layer, and two electrodes disposed on the thermally conductive substrate. The electrically conductive layer is disposed on a first surface of the thermally conductive substrate, and is electrically connected to the electrodes. The LED die module and the LED driving component are welded on the electrically conductive layer to establish an electrical connection therebetween. The packaged body is integrally formed as one body on the first surface to cover the LED die module and the LED driving component. The LED die module is packaged in the packaged body. Thus, the two electrodes are configured to electrically connect to an external power source for directly turning on the LED die module.

Abstract: A method, computer-readable medium, and semiconductor device for securing integrated engineering analysis are provided. A die ID is generated from a lot ID, wafer ID, die coordinates, or other product information. The die ID is encrypted with a key and written to the die. The encryption key and encrypted die ID may be stored in a secure storage. A die is fabricated with an encryption module and an unencrypted die ID. The encryption module is provided with an unencrypted die ID, encrypts the unencrypted die ID, and writes the encrypted die ID to a die fuse.

Abstract: A personal video recorder (PVR) system includes a processing unit, a system memory coupled to the processing unit by a system memory bus, and an insertion module being coupled to the processing unit for inserting a packet into a PVR bit stream according to packet information. During a packet insertion operation, the processing unit is for reading data from the system memory, processing the data to generate the packet insertion information, and directly transferring the packet insertion information to the insertion module. By directly transferring the packet insertion information generated by the processing unit to the insertion module, memory bandwidth requirements of the system memory are reduced, and data access of the system memory is improved.

Abstract: A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer.

Abstract: A circuit board mounting apparatus includes a circuit board, a first mounting member, a second mounting member, and a third mounting member. The first and second mounting members are mounted to a front side of the circuit board. The third mounting member is mounted to a rear side of the circuit board. The circuit board is capable of being mounted to a first side plate of a first chassis in a perpendicular manner by the first and second mounting members, or is capable of being mounted to a second side plate of a second chassis in a parallel manner by the first, second, and third mounting members.

Abstract: A circuit board mounting apparatus includes a chassis and a circuit board. The chassis includes a side plate defining a slide slot and a latching hole. A latch protrudes forward from the circuit board, and includes a neck and a latching portion extending left from a front end of the neck. A cutout is defined in a front side of the circuit board. A cantilever extends into the cutout. A hook protrudes forward from the cantilever. The latch extends through the slide slot to allow the neck to abut against a portion of the side plate bounding a left end of the slide slot, and to allow the latching portion to engage with a front side of the side plate. The cantilever resists the hook to engage in the latching hole and abut against a portion of the side plate bounding a right end of the latching hole.

Abstract: A circuit board mounting apparatus includes a side plate, a circuit board, and a mounting member. The side plate defines a slide slot and a latching hole. A latch protrudes forward from the circuit board, and includes a neck and a latching portion extending leftward from a front end of the neck. The mounting member is mounted to the circuit board, and includes a resilient arm and a hook protruding forward from the resilient arm. The latch extends through the slide slot to allow the neck to abut against a portion of the side plate bounding a left end of the slide slot, and to allow the latching portion to engage with a front side of the side plate. The resilient arm biases the hook to engage in the latching hole and abut against a portion of the side plate bounding a right end of the latching hole.

Abstract: A circuit board mounting apparatus includes a circuit board, a chassis, a first mounting member, a second mounting member, and a fastener. The chassis includes a side plate defining a through hole, a first hole, and a second hole communicating with the first hole. Each of the first and second mounting members includes two latching legs detachably mounted to a front end of the circuit board. A neck protrudes from a front end of the first mounting member, and a head is formed on a front end of the neck. The neck extends through the first hole and engages in the second hole. The head abuts a front side of the side plate. A fixing hole is defined in a front end of the second mounting member. The fastener extends through the through hole and engages in the fixing hole, to mount the circuit board to the side plate.

Abstract: Techniques are described for facilitating transactions involving items and users in various ways. In some situations, item transactions are coordinated by an automated Item Transaction (or “IT”) system provided via one or more computing systems, such that users of the IT system who have available items are matched with other users of the IT system who desire those items. The types of items being involved in transactions via the IT system may vary, and in some situations may include items such as music CDs, video DVDs, computer games, computer software, etc. The operation of the IT system may be enhanced in various ways, including by selecting appropriate users to receive opportunities to sell items available from those users, such as in a manner to balance supply and demand for items, and by notifying the selected users of those opportunities.

Abstract: A dual screen electronic device includes a main device having a first casing and a display screen, and a detachable display module. The first casing has a first opening. The display screen is located on the first casing and exposed from the first opening. The detachable display module includes a second casing, a power supply module, an electrophoretic display (EPD) module, and a control module. The second casing is detachably positioned on the first casing, and has a second opening. The power supply module is arranged on the second casing. The EPD module is fixed to the second casing, or is detachably positioned on the second casing, and has a display region exposed from the second opening. The control module is selectively located on the second casing or on the EPD module, and is electrically connected to the EPD module and the power supply module.

Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.