Abstract: A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature. While the NVM array is heated to the target temperature, a current distribution is obtained by measuring a plurality of currents of a subset of NVM cells of the NVM array, each NVM cell of the NVM array is programmed to one of a logically high state or a logically low state, and first and second pass/fail (P/F) tests on each NVM cell of the NVM array are performed. A bit error rate is calculated based on the current distribution and the first and second P/F tests.

Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to determining that the CSP is solvable and has a solution satisfying the constraints, the at least one fail bit is repaired using the available repair resource in accordance with the solution of the CSP.

Abstract: A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to determining that the CSP is solvable and has a solution satisfying the constraints, the at least one fail bit is repaired using the available repair resource in accordance with the solution of the CSP.

Abstract: A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature. While the NVM array is heated to the target temperature, a current distribution is obtained by measuring a plurality of currents of a subset of NVM cells of the NVM array, each NVM cell of the NVM array is programmed to one of a logically high state or a logically low state, and first and second pass/fail (P/F) tests on each NVM cell of the NVM array are performed. A bit error rate is calculated based on the current distribution and the first and second P/F tests.

Abstract: The present invention provides a group of specific probes directed to cleavage site of hemagglutinin precursor protein of avian influenza virus subtypes H5, and provides a method for rapid pathotyping of H5 avian influenza virus. The present invention further provides a kit containing the probes and the kit is easy-to-use, low-cost, high sensitivity, enabled the molecular pathotyping of H5 viruses by a simpler and faster means that conventional methods.

Abstract: A surface capacitive touch panel including a panel body, four electrodes, a power supply module, a grounding and measuring module, and a computation control module. The electrodes are disposed on four sides of the panel body, respectively, and each have a first end portion and a second end portion. In response to a control signal, the power supply module selects one of the electrodes to function as an electrode under test. The power supply module connects with the first end portion of the electrode under test to supply a power to the electrode under test. The grounding and measuring module connects with the second end portion of the electrode under test to create a grounded loop for measuring currents under test. The computation control module computes touch coordinate positions with values of currents under test measured at the electrodes. Hence, single-touch and multi-touch coordinate positions are accurately determined.

Abstract: A surface capacitive touch panel including a panel body, four electrodes, a power supply module, a grounding and measuring module, and a computation control module. The electrodes are disposed on four sides of the panel body, respectively, and each have a first end portion and a second end portion. In response to a control signal, the power supply module selects one of the electrodes to function as an electrode under test. The power supply module connects with the first end portion of the electrode under test to supply a power to the electrode under test. The grounding and measuring module connects with the second end portion of the electrode under test to create a grounded loop for measuring currents under test. The computation control module computes touch coordinate positions with values of currents under test measured at the electrodes. Hence, single-touch and multi-touch coordinate positions are accurately determined.

Abstract: The present invention provides a group of specific probes directed to cleavage site of hemagglutinin precursor protein of avian influenza virus subtypes H5, and provides a method for rapid pathotyping of H5 avian influenza virus. The present invention further provides a kit containing the probes and the kit is easy-to-use, low-cost, high sensitivity, enabled the molecular pathotyping of H5 viruses by a simpler and faster means that conventional methods.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.

Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

Abstract: A wireless charging holder and an assembly of an electronic device and the wireless charging holder are provided. The wireless charging holder includes a body, a fixing element, a power line, a first coil, and a first magnetic element. The body is used to hold the electronic device. The fixing element has a first end connecting with the body and a second end fixed on a vehicle. The power line has a third end connecting with the body and a fourth end to plug into a socket. The first coil on the body is electronically connected with the power line. The first magnetic element disposed in the body is adjacent to the first coil. The electronic device having a second coil is fixed by the first magnetic element on the body, and the first coil overlaps the second coil to induce current for charging the electronic device.

Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

Abstract: The present invention discloses a manufacturing method of a junction field effect transistor (JFET). The manufacturing method includes: providing a substrate with a first conductive type, forming a channel region with a second conductive type, forming a field region with the first conductive type, forming a gate with the first conductive type, forming a source with the second conductive type, forming a drain with the second conductive type, and forming a lightly doped region with the second conductive type. The channel region is formed by an ion implantation process step, wherein the lightly doped region is formed by masking a predetermined region from accelerated ions of the ion implantation process step, and diffusing impurities with the second conductive type nearby the predetermined region into it with a thermal process step.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

Abstract: The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer.