Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

Abstract: A method for reducing contaminants in a semiconductor device is provided. The method includes cleaning the semiconductor substrate. The cleaning includes rotating the semiconductor substrate and dispersing an aerosol at a predetermined temperature to a surface of the semiconductor substrate or a layer formed on the substrate to be cleaned. The aerosol includes a chemical having a predetermined pressure and a gas having a predetermined flow rate.

Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes conductive lines having sidewalls angled between about 45° to about 90° relative to a plane in which bottom surfaces of the conductive lines lie. A dielectric layer is formed over the conductive lines, where forming the dielectric layer after the conductive lines are formed mitigates damage to the dielectric layer, such as by not subjecting the dielectric layer to etching. The angled sidewalls of the conductive lines cause the dielectric layer to pinch off before an area between adjacent conductive lines is filled, thus establishing an air gap between adjacent conductive lines, where the air gap has a lower dielectric constant than the dielectric material. At least one of the substantially undamaged dielectric layer or the air gap serves to reduce parasitic capacitance within the semiconductor arrangement, which improves performance.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A metal-forming (MF) layer is deposited on the substrate. A radiation exposure process through a photomask is applied to the MF layer to form exposed regions and unexposed regions in the MF layer. The MF layer in the unexposed regions is removed while the MF layer in the exposed regions remains to form metal features. A dielectric layer is deposited to fill in regions between metal features.

Abstract: Among other things, one or more techniques for forming a low k dielectric around a metal line during an integrated circuit (IC) fabrication process are provided. In an embodiment, a metal line is formed prior to forming a surrounding low k dielectric layer around the metal line. In an embodiment, the metal line is formed by filling a trench space in a skeleton layer with metal. In this embodiment, the skeleton layer is removed to form a dielectric space in a different location than the trench space. The dielectric space is then filled with a low k dielectric material to form a surrounding low k dielectric layer around the metal line. In this manner, damage to the surrounding low k dielectric layer, that would otherwise occur if the surrounding low k dielectric layer was etched, for example, is mitigated.

Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.

Abstract: A data storage system comprises at least one data storage module, each data storage module having at least a first I/O port and a second I/O port, wherein the data storage module includes a storage medium having at least a first pre-partitioned area and a second pre-partitioned area. The data storage system further comprises a first controller module, which is directly connected to the first I/O port of each data storage module to access the first pre-partitioned area of each data storage module, and a second controller module, which is directly connected to the second I/O port of each data storage module to access the second pre-partitioned area of each data storage module.

Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

Abstract: A prefabricated wall or floor panel includes a rectangular concrete section comprising a projection along one side, a recess along the other side, the recessing being complementary to the projection, a protrusion along one end, a trough along the other end, the trough being complementary to the protrusion, channels each having one end terminated at one end and the other end terminated at the other end, a first groove on each of one end and the other end extending from one side to the other side by passing the mouths of the channels, and a second groove on either side extending from one end to the other end; a rectangular surface board formed integrally with an outer surface of the concrete section; and an interconnection comprising a transverse part of and spaced longitudinal tubes each adapted to fit into the channel to connect two adjacent prefabricated components together.

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract: A system and method for simulating aging parameters of a System-on-Chip (SoC) integrated circuit is disclosed. A SoC integrated circuit is first divided into a plurality of blocks in accordance with the nature or the operating conditions of each block. The simulation of a digital circuit based block is performed by a static timing analyzer. The simulation of a mixed signal based block is performed by first employing a fresh device model to obtain relevant operation conditions, such as node voltages. Based upon the operation conditions and reliability characterization data, parameters degradation calculators assess aging characteristic factors of each block. In a subsequent simulation, a circuit simulator calculates the design corners of a SoC chip based upon the characteristic factors of each block.

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract: A power supply device and a wireless communication system are provided. The power supply device includes a data input port, a power over Ethernet control module, a network port, a decoder circuit and a signal strength indicator unit. The power over Ethernet control module is configured for receiving a data signal from the data input port to generate a data signal with power. The network port is configured for transmitting the data signal with power to the main board and receiving a signal in relation to a signal receiving strength state of the wireless communication device. The decoder circuit is connected to the network port and configured for generating a signal strength indicator signal. The signal strength indicator unit is connected to the decoder circuit and configured for receiving the signal strength indicator signal to display the signal receiving strength state of the wireless communication device.

Abstract: A prefabricated wall or floor panel includes a rectangular concrete section comprising a projection along one side, a recess along the other side, the recessing being complementary to the projection, a protrusion along one end, a trough along the other end, the trough being complementary to the protrusion, channels each having one end terminated at one end and the other end terminated at the other end, a first groove on each of one end and the other end extending from one side to the other side by passing the mouths of the channels, and a second groove on either side extending from one end to the other end; a rectangular surface board formed integrally with an outer surface of the concrete section; and an interconnection comprising a transverse part of and spaced longitudinal tubes each adapted to fit into the channel to connect two adjacent prefabricated components together.

Abstract: A signal transferring device adapted to connect to a communication device via a network cable, includes a network port, a third port, a decoder circuit and a signal strength indicator unit. The network port is connected to a communication device via a network cable. The third port is different from the network port and connected to a plurality of signal lines and a ground line of a main board of the communication device via the network port. The decoder circuit is connected to a power line, a ground line and at least one first control line of the main body to receiving a signal in relation to a signal receiving strength state of the communication device for generating a signal strength indicator signal. The signal strength indicator unit is connected to the decoder circuit and configured for displaying the signal receiving strength state of the communication device.

Abstract: A word line control device has a word line driver for deactivating and activating a word line to control access to a memory cell, and a voltage coupling device for coupling voltages to the word line driver. The word line control device maintains boosted voltages and has significantly reduced leakage currents and power consumption in the active and standby modes.

Abstract: A power supply device and a wireless communication system are provided. The power supply device includes a data input port, a power over Ethernet control module, a network port, a decoder circuit and a signal strength indicator unit. The power over Ethernet control module is configured for receiving a data signal from the data input port to generate a data signal with power. The network port is configured for transmitting the data signal with power to the main board and receiving a signal in relation to a signal receiving strength state of the wireless communication device. The decoder circuit is connected to the network port and configured for generating a signal strength indicator signal. The signal strength indicator unit is connected to the decoder circuit and configured for receiving the signal strength indicator signal to display the signal receiving strength state of the wireless communication device.

Abstract: A signal transferring device adapted to connect to a communication device via a network cable, includes a network port, a third port, a decoder circuit and a signal strength indicator unit. The network port is connected to a communication device via a network cable. The third port is different from the network port and connected to a plurality of signal lines and a ground line of a main board of the communication device via the network port. The decoder circuit is connected to a power line, a ground line and at least one first control line of the main body to receiving a signal in relation to a signal receiving strength state of the communication device for generating a signal strength indicator signal. The signal strength indicator unit is connected to the decoder circuit and configured for displaying the signal receiving strength state of the communication device.

Abstract: A method and a system for correcting a soft error in a memory circuit operates during a stand-by mode. After reading data from at least one memory cell without outputting the read data through an input/output module of the memory circuit in the stand-by mode, it is determined whether the read data is a soft error. If so, a correct value is written to the memory cell if the read data is the soft error.