Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a warpage-control element attached to the circuit substrate. The warpage-control element has a protruding portion extending into the circuit substrate. The warpage-control element has height larger than that of the die package.

Abstract: The present application relates to the technical field of semiconductors, and in particular, to a wafer scheduling method and a wafer scheduling apparatus for an etching equipment. The wafer scheduling method includes: obtaining a wafer processing request, where the wafer processing request includes at least process information of wafers and an equipment processing parameter of the etching equipment; responding to the wafer processing request, and determining a wafer scheduling parameter corresponding to the process information and the equipment processing parameter, based on the process information, the equipment processing parameter, and a preset wafer scheduling policy, where the wafer scheduling parameter is used to determine a transfer time for transferring the wafers to the etching equipment for processing; and performing wafer scheduling processing on the wafers by using the wafer scheduling parameter. In this way, the wafer processing productivity of the etching equipment can be improved.

Abstract: A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.

Abstract: A package assembly includes a package substrate, a package lid located on the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot having a height greater than or equal to a height of the outer foot, extending from the plate portion and including a first inner foot corner portion located inside a first corner of the outer foot, and an adhesive that adheres the outer foot to the package substrate and adheres the inner foot to the package substrate.

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: An electrophoretic display and a driving method thereof are provided. The electrophoretic display includes a display panel and a driving circuit. The display panel includes an electrophoretic unit and a driving substrate. The electrophoretic unit includes a plurality of electrophoretic particles. The driving substrate is disposed below the electrophoretic unit. The driving circuit is coupled to the driving substrate. The driving circuit sequentially provides a first reset signal and a second reset signal to the driving substrate during a reset period to reset the plurality of electrophoretic particles. The first reset signal sequentially includes a first sub-balanced signal and a first sub-mixed signal. The second reset signal sequentially includes a second sub-balanced signal and a second sub-mixed signal.

Abstract: A method of fabricating a semiconductor device includes recessing an upper portion of a first dielectric layer disposed over a conductive feature. The method includes filling the recessed upper portion with a second dielectric layer to form a void embedded in the second dielectric layer. The method includes etching the second dielectric layer and the first dielectric layer to form a contact opening that exposes at least a portion of the conductive feature using the void to vertically align at least a lower portion of the contact opening with the conductive feature. The method includes filling the contact opening with a conductive material to form a contact feature electrically coupled to the conductive feature.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

Abstract: A lens assembly includes a first lens group, a second lens group, a third lens group, a fourth lens group, and a reflective element. The first lens group is with refractive power. The second lens group is with positive refractive power. The third lens group is with positive refractive power. The fourth lens group is with refractive power. The reflective element includes a reflective surface. A light from an object sequentially passes through the first lens group, the second lens group, the third lens group, and the fourth lens group to an image side along an axis. The reflective element is disposed between an object side and the image side along the axis. Intervals of the lens groups are changeable when the lens assembly zooms from a wide-angle end to a telephoto end.

Abstract: A battery assembly includes a battery holding unit and a battery unit removably held by the battery holding unit. The battery unit includes a battery, a first engaging portion, and a second engaging portion. The battery holding unit includes a holding member selectively engaged with the first engaging portion or the second engaging portion to hold the battery unit at a first position or a second position. When the holding member and the first engaging portion relatively move away from each other along a disengagement direction, the battery unit moves along a detachment direction from the first position to the second position at which the holding member engages with the second engaging portion, and the second engaging portion is allowed to move to disengage from the holding member, so that the battery unit moves again along the detachment direction to be removed from the battery holding unit.

Abstract: A training apparatus and a training method for providing a sample size expanding model are provided. A normalizing unit receives a training data set with at least one numeric predictor factor and a numeric response factor. An encoding unit trains the training data set in an initial encoding layer and at least one deep encoding layer. A modeling unit extracts a mean vector and a variance vector and inputting the mean vector and the variance vector together into a latent hidden layer for obtaining the sample size expanding model. A decoding unit trains the training data set in at least one deep decoding layer and a last encoding layer. A verifying unit performs a verification of the sample size expanding model according to the outputting data set. A data generating unit generates a plurality of samples via the sample size expanding model.

Abstract: Therapeutic combinations of hepatitis B virus (HBV) vaccines and a pyridopyrimidine derivative are described. Methods of inducing an immune response against HBV or treating an HBV-induced disease, particularly in individuals having chronic HBV infection, using the disclosed therapeutic combinations are also described. The invention provides therapeutic combinations or compositions and methods for inducing an immune response against hepatitis B viruses (HBV) infection.

Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.

Abstract: A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.