Patents by Inventor Chien-Tai Chan
Chien-Tai Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8895383Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.Type: GrantFiled: April 16, 2013Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Da-Wen Lin, Hsien-Chin Lin
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Patent number: 8884341Abstract: An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.Type: GrantFiled: August 16, 2011Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Su-Hao Liu, Chien-Tai Chan, King-Yuen Wong, Chien-Chang Su
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Patent number: 8785286Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.Type: GrantFiled: February 9, 2010Date of Patent: July 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
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Patent number: 8759943Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).Type: GrantFiled: October 8, 2010Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Tseng, Da-Wen Lin, Chien-Tai Chan, Chia-Pin Lin, Li-Wen Weng, An-Shen Chang, Chung-Cheng Wu
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Patent number: 8703593Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.Type: GrantFiled: June 14, 2013Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
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Publication number: 20130280876Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
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Patent number: 8426923Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.Type: GrantFiled: June 9, 2010Date of Patent: April 23, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Da-Wen Lin, Hsien-Chin Lin
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Publication number: 20130043511Abstract: An integrated circuit includes a gate electrode disposed over a substrate. A source/drain (S/D) region is disposed adjacent to the gate electrode. The S/D region includes a diffusion barrier structure disposed in a recess of the substrate. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode. The second portion is distant from the gate electrode. An N-type doped silicon-containing structure is disposed over the diffusion barrier structure. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate. The second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.Type: ApplicationFiled: August 16, 2011Publication date: February 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung TSAI, Su-Hao LIU, Chien-Tai CHAN, King-Yuen WONG, Chien-Chang SU
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Patent number: 8357579Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.Type: GrantFiled: March 8, 2011Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Ming-Lung Cheng, Chien-Tai Chan, Da-Wen Lin, Chung-Cheng Wu
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Publication number: 20120135575Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.Type: ApplicationFiled: March 8, 2011Publication date: May 31, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: King-Yuen WONG, Ming-Lung CHENG, Chien-Tai CHAN, Da-Wen LIN, Chung-Cheng WU
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Patent number: 8187928Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in an ambient with an oxygen-containing chemical.Type: GrantFiled: September 21, 2010Date of Patent: May 29, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: De-Wei Yu, Chun Hsiung Tsai, Yu-Lien Huang, Chien-Tai Chan, Wen-Sheh Huang
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Publication number: 20120086053Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).Type: ApplicationFiled: October 8, 2010Publication date: April 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hung TSENG, Da-Wen LIN, Chien-Tai CHAN, Chia-Pin LIN, Li-Wen WENG, An-Shen CHANG, Chung-Cheng WU
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Publication number: 20120070953Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in an ambient with an oxygen-containing chemical.Type: ApplicationFiled: September 21, 2010Publication date: March 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: De-Wei YU, Chun Hsiung TSAI, Yu-Lien HUANG, Chien-Tai CHAN, Wen-Sheh HUANG
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Publication number: 20110295539Abstract: A method for measuring the intra-die temperature of a wafer with a fast response time is described. The method includes providing a wafer in a thermal process chamber, radiating the wafer in a first predetermined radiation range to heat the wafer to a predetermined temperature range for a predetermined time, receiving the radiation reflected from a die area while the wafer is being heated and detecting reflected radiation having a second predetermined radiation range, and determining a temperature of the die area by a processor being responsive to the detected second predetermined radiation range.Type: ApplicationFiled: May 28, 2010Publication date: December 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung TSAI, Chii-Ming WU, De-Wei YU, Chien-Tai CHAN
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Publication number: 20110248322Abstract: An embodiment is a semiconductor device. The semiconductor device comprises a substrate, an electrode over the substrate, and a piezoelectric layer disposed between the substrate and the electrode. The piezoelectric layer causes a strain in the substrate when an electric field is generated by the electrode.Type: ApplicationFiled: April 12, 2010Publication date: October 13, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Chien-Tai Chan, Da-Wen Lin, Chung-Cheng Wu
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Publication number: 20110227162Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.Type: ApplicationFiled: March 17, 2010Publication date: September 22, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pin LIN, Chien-Tai CHAN, Hsien-Chin LIN, Shyue-Shyh LIN
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Publication number: 20110210393Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.Type: ApplicationFiled: March 1, 2010Publication date: September 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Kai Chen, Hsien-Hsin Lin, Chia-Pin Lin, Chien-Tai Chan, Yuan-Ching Peng
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Publication number: 20110195555Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.Type: ApplicationFiled: February 9, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
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Patent number: 7994016Abstract: A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.Type: GrantFiled: November 11, 2009Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsiung Tsai, Chun-Feng Nieh, Da-Wen Lin, Chien-Tai Chan
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Publication number: 20110127610Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.Type: ApplicationFiled: June 9, 2010Publication date: June 2, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Da-Wen Lin, Hsien-Chin Lin