Patents by Inventor Chih-Chang Lin
Chih-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170126230Abstract: A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.Type: ApplicationFiled: January 12, 2017Publication date: May 4, 2017Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
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Patent number: 9601489Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.Type: GrantFiled: December 4, 2015Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Hong Chern, Chih-Chang Lin, Julie Tran, Jacklyn Chang
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Publication number: 20170061447Abstract: A marketing system of collecting and exchanging point includes a server side device, a plurality of shop side devices, and a plurality of consumption side devices. The server side device stores shop accounts, information of collecting and exchanging point, customer accounts, and customer point information. Each shop side device is respectively corresponding to one shop account. Each consumption side device is respectively corresponding to one customer account. Each consumption side device respectively has a point collecting module and a point exchanging module for executing a point collecting action and a point exchanging action. The server side device gathers and computes exchangeable points being collected and exchanged with regard to a plurality of the shop accounts. The exchangeable points of the customer account are divided into a plurality of exchangeable points specialized for each of the shop accounts.Type: ApplicationFiled: August 27, 2015Publication date: March 2, 2017Inventors: Fu-Kuang Wang, Hsiang-Chun Tseng, Li-Hua Huang, Chih-Chang Lin, Chin-Yu Chen
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Patent number: 9584107Abstract: A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal.Type: GrantFiled: November 26, 2014Date of Patent: February 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching (Jim) Huang, Chih-Chang Lin, Tien-Chun Yang
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Patent number: 9570977Abstract: An initialization device for a charge pump includes a driving circuit and a bias voltage circuit. The driving circuit is between two power supply nodes. The driving circuit includes a first node configured to be coupled to an output electrode of a capacitor in the charge pump. The bias voltage circuit is coupled to the two power supply nodes. The bias voltage circuit includes a second node coupled to a control terminal of the driving circuit. In response to an applied initialization signal, the bias voltage circuit is configured to output a bias voltage to the second node. The bias voltage has at least two levels that correspond to levels of the applied initialization signal. In response to the bias voltage, the driving circuit is configured to output an output signal having at least two levels that correspond to the at least two levels of the bias voltage.Type: GrantFiled: November 20, 2015Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Chih-Chang Lin, Tsung-Ching Huang, Ming-Chieh Huang
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Patent number: 9559686Abstract: A circuit includes a first power node, a second power node, an output node, a plurality of first transistors and a plurality of second transistors. The plurality of first transistors is serially coupled between the first power node and the output node. The plurality of second transistors is serially coupled between the second power node and the output node.Type: GrantFiled: November 18, 2015Date of Patent: January 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
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Patent number: 9531350Abstract: An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level.Type: GrantFiled: April 9, 2013Date of Patent: December 27, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Chih-Chang Lin, Yuwen Swei, Ming-Chieh Huang
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Publication number: 20160359475Abstract: A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.Type: ApplicationFiled: August 23, 2016Publication date: December 8, 2016Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
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Patent number: 9509260Abstract: A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to receive an input signal. A second inverter has a second input node and a second output node. The second input node connects to a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. A first amplifier is configured to provide feedback to the first input node and a second amplifier is configured to provide feedback to the second input node.Type: GrantFiled: October 1, 2014Date of Patent: November 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching Huang, Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin
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Patent number: 9502098Abstract: A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator.Type: GrantFiled: February 3, 2016Date of Patent: November 22, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
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Patent number: 9503252Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.Type: GrantFiled: January 27, 2014Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen (David) Chung, Tsung-Ching (Jim) Huang, Chih-Chang Lin
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Patent number: 9489989Abstract: A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.Type: GrantFiled: June 22, 2010Date of Patent: November 8, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
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Patent number: 9461539Abstract: A voltage regulator includes a driving circuit, a feedback circuit, first and second control circuits and a resistor. The driving circuit is coupled to an input node and an output node and generates an output voltage at the output node from an input voltage at the input node. The feedback circuit is coupled to the output node and generates a feedback voltage based on the output voltage. The first control circuit is coupled to the feedback circuit and the driving circuit to control the output voltage based on the feedback voltage. The resistor has opposite first and second terminals. The first terminal of the resistor is coupled to the output node. The second control circuit is coupled to the second terminal of the output stage resistor and the feedback circuit to control the feedback voltage based on a regulated voltage at the second terminal of the resistor.Type: GrantFiled: March 15, 2013Date of Patent: October 4, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching (Jim) Huang
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Patent number: 9455666Abstract: A circuit includes at least two LC voltage controlled oscillators (LCVCOs). Each LCVCO includes a switch to selectively turn on or off the LCVCO. One selected LCVCO of the at least two LCVCOs is configured to provide a differential LCVCO output. A converter coupled to the at least two LCVCOs is configured to receive the differential LCVCO output and provide an output signal with a full voltage swing.Type: GrantFiled: February 13, 2015Date of Patent: September 27, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Lin, Chan-Hong Chern, Ming-Chieh Huang, Tien-Chun Yang
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Publication number: 20160277014Abstract: A clock generation circuit includes a two-phase non-overlapping clock generation circuit, an inverter, and a delay circuit. The two-phase non-overlapping clock generation circuit is configured to generate a first phase clock signal and a second phase clock signal based on a non-inverted clock signal and an inverted clock signal. The first phase clock signal and the second phase clock signal correspond to a same logical value during a first duration and a second duration within a clock cycle. The inverter is configured to generate the inverted clock signal based on an input clock signal. The delay circuit is configured to generate the non-inverted clock signal based on the input clock signal. The delay circuit has a predetermined delay sufficient to cause a difference between the first duration and the second duration to be less than a predetermined tolerance.Type: ApplicationFiled: January 21, 2016Publication date: September 22, 2016Inventors: Tien-Chun YANG, Chih-Chang LIN, Ming-Chieh HUANG
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Patent number: 9450789Abstract: An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights.Type: GrantFiled: July 9, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Jing Jing Chen, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Yuwen Swei
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Patent number: 9450573Abstract: A circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal.Type: GrantFiled: February 25, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
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Publication number: 20160248330Abstract: A voltage supply unit includes a regulator unit, a current mirror, and a cascode unit. The regulator unit is configured to receive first and second voltage signals and generate a third voltage signal. The current mirror is configured to generate first and second current signals based on the third voltage signal. The cascode unit includes a first terminal configured to receive the first current signal, a second terminal configured to receive a first bias voltage signal, a third terminal configured to receive a second bias voltage signal, and a fourth terminal electrically connected to the regulator unit. An output voltage supply signal is controlled by the second current signal.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
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Publication number: 20160248411Abstract: A circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal.Type: ApplicationFiled: February 25, 2015Publication date: August 25, 2016Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
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Patent number: RE46336Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.Type: GrantFiled: May 14, 2014Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chang Lin, Chan-Hong Chern, Steven Swei, Ming-Chieh Huang, Tien-Chun Yang