Patents by Inventor Chih-Chieh Cheng
Chih-Chieh Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10340876Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors. Some embodiments integrate one or more filter circuits with a tunable impedance matching network, useful in conjunction with such applications as radio frequency power amplifiers.Type: GrantFiled: February 19, 2016Date of Patent: July 2, 2019Assignee: pSemi CorporationInventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
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Publication number: 20190140602Abstract: An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.Type: ApplicationFiled: July 6, 2018Publication date: May 9, 2019Inventors: Tero Tapio Ranta, Chih-Chieh Cheng, Kevin Roberts
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Patent number: 10284151Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.Type: GrantFiled: February 13, 2018Date of Patent: May 7, 2019Assignee: pSemi CorporationInventors: Hossein Noori, Chih-Chieh Cheng
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Publication number: 20190020316Abstract: A ultra-compact coupler designed to sample the actual output power of a power amplifier and which is “VSWR insensitive”, such that reflected power is essentially not coupled to a detector circuit and only forward power is detected and processed. In a first embodiment, a coupler is situated between the final amplifier stage of a power amplifier and an output impedance matching network, and is specially configured for operation in a low impedance environment in conjunction with a detector circuit, thereby substantially reducing the areal size of the coupler. In a second embodiment, a coupler is integrated within an output impedance matching network coupled to the final amplifier stage of a power amplifier so as to share an inductor between the coupler and the output impedance matching network, thereby further substantially reducing the areal size of the coupler.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: Chih-Chieh Cheng, Tero Tapio Ranta
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Patent number: 10181823Abstract: A ultra-compact coupler designed to sample the actual output power of a power amplifier and which is “VSWR insensitive”, such that reflected power is essentially not coupled to a detector circuit and only forward power is detected and processed. In a first embodiment, a coupler is situated between the final amplifier stage of a power amplifier and an output impedance matching network, and is specially configured for operation in a low impedance environment in conjunction with a detector circuit, thereby substantially reducing the areal size of the coupler. In a second embodiment, a coupler is integrated within an output impedance matching network coupled to the final amplifier stage of a power amplifier so as to share an inductor between the coupler and the output impedance matching network, thereby further substantially reducing the areal size of the coupler.Type: GrantFiled: July 17, 2017Date of Patent: January 15, 2019Assignee: pSemi CorporationInventors: Chih-Chieh Cheng, Tero Tapio Ranta
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Publication number: 20190013790Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.Type: ApplicationFiled: July 6, 2018Publication date: January 10, 2019Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
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Patent number: 10141927Abstract: A switch architecture having open reflective unselected ports. Signals can be selectively coupled between a common port and at least one selectable port through series connected switches. When one or more port is selected, the remaining ports are opened. In addition, associated “shuntable” switches from each of the selectable ports to ground are always open, regardless of the ON or OFF state of the series switches; thus, there is no normally active connection of the selectable ports to ground, but the presence of the shuntable switches provides electrostatic discharge protection for all ports. Embodiments of the invention allow configurability between a traditional architecture and an open reflective unselected port architecture, and include integrated circuit and field effect transistor embodiments.Type: GrantFiled: April 27, 2017Date of Patent: November 27, 2018Assignee: pSemi CorporationInventors: Tero Tapio Ranta, Chih-Chieh Cheng
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Patent number: 10141958Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters also include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may also be included on the common port of the multi-path RF switch to provide additional impedance matching capability.Type: GrantFiled: February 19, 2016Date of Patent: November 27, 2018Assignee: pSemi CorporationInventors: Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
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Patent number: 10038414Abstract: An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.Type: GrantFiled: December 7, 2016Date of Patent: July 31, 2018Assignee: pSemi CorporationInventors: Tero Tapio Ranta, Chih-Chieh Cheng, Kevin Roberts
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Publication number: 20180175807Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.Type: ApplicationFiled: February 13, 2018Publication date: June 21, 2018Inventors: Hossein Noori, Chih-Chieh Cheng
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Publication number: 20180159486Abstract: An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.Type: ApplicationFiled: December 7, 2016Publication date: June 7, 2018Inventors: Tero Tapio Ranta, Chih-Chieh Cheng, Kevin Roberts
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Patent number: 9929701Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.Type: GrantFiled: September 21, 2016Date of Patent: March 27, 2018Assignee: pSemi CorporationInventors: Hossein Noori, Chih-Chieh Cheng
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Publication number: 20180083579Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.Type: ApplicationFiled: September 21, 2016Publication date: March 22, 2018Inventors: Hossein Noori, Chih-Chieh Cheng
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Patent number: 9830992Abstract: An operation method of a memory cell includes steps of applying a pre pulse before a read pulse is applied, wherein the pre pulse is larger than a maximum threshold voltage or less than a lowest threshold voltage.Type: GrantFiled: November 28, 2016Date of Patent: November 28, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Wen-Jer Tsai, Wei-Liang Lin, Chih-Chieh Cheng
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Publication number: 20170302272Abstract: A switch architecture having open reflective unselected ports. Signals can be selectively coupled between a common port and at least one selectable port through series connected switches. When one or more port is selected, the remaining ports are opened. In addition, associated “shuntable” switches from each of the selectable ports to ground are always open, regardless of the ON or OFF state of the series switches; thus, there is no normally active connection of the selectable ports to ground, but the presence of the shuntable switches provides electrostatic discharge protection for all ports. Embodiments of the invention allow configurability between a traditional architecture and an open reflective unselected port architecture, and include integrated circuit and field effect transistor embodiments.Type: ApplicationFiled: April 27, 2017Publication date: October 19, 2017Inventors: Tero Tapio Ranta, Chih-Chieh Cheng
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Patent number: 9786794Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: GrantFiled: April 11, 2016Date of Patent: October 10, 2017Assignee: MACRONIX International Co., Ltd.Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
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Publication number: 20170244432Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters also include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may also be included on the common port of the multi-path RF switch to provide additional impedance matching capability.Type: ApplicationFiled: February 19, 2016Publication date: August 24, 2017Inventors: Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
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Patent number: 9667246Abstract: A switch architecture having open reflective unselected ports. Signals can be selectively coupled between a common port and at least one selectable port through series connected switches. When one or more port is selected, the remaining ports are opened. In addition, associated “shuntable” switches from each of the selectable ports to ground are always open, regardless of the ON or OFF state of the series switches; thus, there is no normally active connection of the selectable ports to ground, but the presence of the shuntable switches provides electrostatic discharge protection for all ports. Embodiments of the invention allow configurability between a traditional architecture and an open reflective unselected port architecture, and include integrated circuit and field effect transistor embodiments.Type: GrantFiled: September 30, 2014Date of Patent: May 30, 2017Assignee: Peregrine Semiconductor CorporationInventors: Tero Tapio Ranta, Chih-Chieh Cheng
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Patent number: 9667217Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors.Type: GrantFiled: April 17, 2015Date of Patent: May 30, 2017Assignee: Peregrine Semiconductor CorporationInventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
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Publication number: 20170026021Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors. Some embodiments integrate one or more filter circuits with a tunable impedance matching network, useful in conjunction with such applications as radio frequency power amplifiers.Type: ApplicationFiled: February 19, 2016Publication date: January 26, 2017Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar