Patents by Inventor Chih-Chieh Cheng
Chih-Chieh Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160308506Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
-
Publication number: 20160225911Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: ApplicationFiled: April 11, 2016Publication date: August 4, 2016Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
-
Publication number: 20160218111Abstract: A memory device is provided. The memory device includes a substrate, a plurality of semiconductor strip structures, a first doped region, a plurality of second doped regions, a plurality of first contacts, and a plurality of second contacts. Each of the semiconductor strip structures extends along a first direction. The first doped region includes a plurality of first portions and a second portion. Each of the first portions is located on a lower part of the corresponding semiconductor strip structure. The second portion is located on a surface of the substrate, and the first portions are connected to the second portion. Each of the second doped regions is located on an upper part of the corresponding semiconductor strip structure. Each of the first contacts is electrically connected to the second portion of the first doped region. Each of the second contacts is electrically connected to the corresponding second doped region.Type: ApplicationFiled: January 23, 2015Publication date: July 28, 2016Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai
-
Patent number: 9385240Abstract: A memory device includes a substrate, a first doped region, composite structures, word lines, and a charge storage layer. The first doped region is disposed on a surface of the substrate. The composite structures are disposed on the first doped region. Each composite structure includes two semiconductor fin structures and a dielectric layer. Each semiconductor fin structure includes a second doped region disposed at an upper portion of the semiconductor fin structure and a body region disposed between the second doped region and the first doped region. The dielectric layer is disposed between the semiconductor fin structures. The word lines are disposed on the substrate. Each word line covers a partial sidewall and a partial top of each composite structure. The charge storage layer is disposed between the composite structures and the word lines.Type: GrantFiled: March 3, 2015Date of Patent: July 5, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai, Nan-Heng Lu
-
Patent number: 9373629Abstract: A memory device is provided. The memory device includes a plurality of stack structures, a plurality of first stepped contacts, and a plurality of second stepped contacts. Each of the stack structures extends in a first direction, and includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is disposed above the first semiconductor layer. Each of the first stepped contacts extends in a second direction, and a bottom surface thereof is electrically connected to the first semiconductor layers of an i+1th stack structure and an i+2th stack structure, wherein i is an odd number. Each of the second stepped contacts extends in the second direction, and a bottom surface thereof is electrically connected to the second semiconductor layers of an nth stack structure and the i+1th stack structure. The first direction is different from the second direction.Type: GrantFiled: January 23, 2015Date of Patent: June 21, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Shih-Guei Yan, Chih-Chieh Cheng, Wen-Jer Tsai
-
Patent number: 9349878Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: GrantFiled: June 24, 2014Date of Patent: May 24, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
-
Patent number: 9269583Abstract: Provided is a method for fabricating a memory device, including the following steps. A plurality of semiconductor fin structures is formed on a substrate. Each semiconductor fin structure includes a first doped region and a body region on which the first doped region is disposed, and a trench is disposed between adjacent two semiconductor fin structures. A second doped region is formed in the substrate under the body regions of the semiconductor fin structures and the trenches. A plurality of first contacts are formed on the substrate. A plurality of second contacts are formed on the substrate. Each second contact is electrically connected with the corresponding first doped region.Type: GrantFiled: October 31, 2014Date of Patent: February 23, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Shih-Guei Yan, Chih-Chieh Cheng, Wen-Jer Tsai
-
Patent number: 9209316Abstract: A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.Type: GrantFiled: March 15, 2012Date of Patent: December 8, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Cheng-Hsien Cheng, Wen-Jer Tsai
-
Patent number: 9209198Abstract: Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.Type: GrantFiled: May 12, 2014Date of Patent: December 8, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai
-
Publication number: 20150325584Abstract: Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.Type: ApplicationFiled: May 12, 2014Publication date: November 12, 2015Applicant: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai
-
Patent number: 9070588Abstract: A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.Type: GrantFiled: August 13, 2014Date of Patent: June 30, 2015Assignee: MACRONIX International Co. Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai
-
Patent number: 9048263Abstract: A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.Type: GrantFiled: June 25, 2014Date of Patent: June 2, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Cheng-Hsien Cheng, Wen-Jer Tsai
-
Publication number: 20150130557Abstract: A switch architecture having open reflective unselected ports. Signals can be selectively coupled between a common port and at least one selectable port through series connected switches. When one or more port is selected, the remaining ports are opened. In addition, associated “shuntable” switches from each of the selectable ports to ground are always open, regardless of the ON or OFF state of the series switches; thus, there is no normally active connection of the selectable ports to ground, but the presence of the shuntable switches provides electrostatic discharge protection for all ports. Embodiments of the invention allow configurability between a traditional architecture and an open reflective unselected port architecture, and include integrated circuit and field effect transistor embodiments.Type: ApplicationFiled: September 30, 2014Publication date: May 14, 2015Inventors: Tero Tapio Ranta, Chih-Chieh Cheng
-
Patent number: 8981459Abstract: A semiconductor structure uses its control gate to be the wordline for receiving an operation voltage for the semiconductor structure. The semiconductor structure has a first and a second doped region and a buried channel between the first and the second doped region, wherein the buried channel has a first length along the first direction. The semiconductor structure further has a charge trapping layer stack on the buried channel and a conductive layer on the charge trapping layer stack, wherein the conductive layer extends along the first direction. The conductive layer is configured as both the control gate and the wordline of the semiconductor structure.Type: GrantFiled: April 24, 2013Date of Patent: March 17, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Shih-Guei Yan, Wen-Jer Tsai, Chih-Chieh Cheng
-
Publication number: 20140346586Abstract: A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai
-
Publication number: 20140308791Abstract: A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.Type: ApplicationFiled: June 25, 2014Publication date: October 16, 2014Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Cheng-Hsien Cheng, Wen-Jer Tsai
-
Publication number: 20140306282Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: ApplicationFiled: June 24, 2014Publication date: October 16, 2014Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang
-
Publication number: 20140264543Abstract: A semiconductor structure uses its control gate to be the wordline for receiving an operation voltage for the semiconductor structure. The semiconductor structure has a first and a second doped region and a buried channel between the first and the second doped region, wherein the buried channel has a first length along the first direction. The semiconductor structure further has a charge trapping layer stack on the buried channel and a conductive layer on the charge trapping layer stack, wherein the conductive layer extends along the first direction. The conductive layer is configured as both the control gate and the wordline of the semiconductor structure.Type: ApplicationFiled: April 24, 2013Publication date: September 18, 2014Applicant: Macronix International Co., Ltd.Inventors: Shih-Guei Yan, Wen-Jer Tsai, Chih-Chieh Cheng
-
Patent number: 8835297Abstract: A fabricating method for fabricating a non-volatile memory structure including the following steps is provided. A first conductive type doped layer is formed in a substrate. A plurality of stacked structures is formed on the substrate, and each of the stacked structures includes a charge storage structure. A first dielectric layer is formed on the substrate between the adjacent stacked structures. A second conductive type doped region is formed in the substrate between the adjacent charge storage structures. The second conductive type doped region has an overlap region with each of the charge storage structures. In addition, the second conductive type doped region divides the first conductive type doped layer into a plurality of first conductive type doped regions that are separated from each other. A conductive layer is formed on the first dielectric layer.Type: GrantFiled: January 25, 2013Date of Patent: September 16, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Chieh Cheng, Shih-Guei Yan, Wen-Jer Tsai
-
Patent number: 8796754Abstract: A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.Type: GrantFiled: June 22, 2011Date of Patent: August 5, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Cheng-Hsien Cheng, Wen-Jer Tsai, Shih-Guei Yan, Chih-Chieh Cheng, Jyun-Siang Huang