Abstract: The present invention provides a novel use of far-infrared radiation for improving patency of arteriovenous fistula, decreasing failure of arteriovenous fistula maturation and preventing and/or ameliorating peripheral artery diseases in a subject in need thereof. The radiation has an electromagnetic wave of about 1.5 to 100 ?m wavelength, which performs on the subject skin surface for more than 10 minutes.

Abstract: A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.

Abstract: A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.

Abstract: A method for reducing a supply voltage drop in a digital circuit block, where the digital circuit block includes a first conducting segment coupled to a first supply voltage, a second conducting segment coupled to a second supply voltage, and a digital logic coupled between the first conducting segment and the second conducting segment, the method including: constructing a third conducting segment connected to the first conducting segment and not electrically connected to the second conducting segment, wherein the third conducting segment is configured to have a first portion located at a first conducting layer; and constructing a fourth conducting segment electrically connected to the second conducting segment and not electrically connected to the first conducting segment, wherein the fourth conducting segment is configured to have a second portion located at a second conducting layer, and whereby a capacitive element is formed between the first portion and the second portion.

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract: A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.

Abstract: A method for fabricating a conductive plug includes the steps of providing a substrate having at least a gate structure thereon, a first dielectric layer covering a surface of the substrate, a second dielectric layer disposed on the first dielectric layer, and at least a metal line formed within the second dielectric layer; forming a hard mask plug on the second dielectric layer; forming a third dielectric layer covering the second dielectric layer and the hard mask plug; removing a portion of the third dielectric layer to expose the hard mask plug; removing the hard mask plug to form a plug hole; and forming the conductive plug within the plug hole to electrically connect with the gate structure.

Abstract: A method for manufacturing collars of deep trench capacitors includes providing a substrate with a deep trench in which there is a trench capacitor in the bottom; forming an inner wall layer completely covering the deep trench and the substrate; forming a hard mask layer on the surface of the inner wall layer; performing a selective implanting but not on the hard mask layer on the wall of the deep trench; performing a selective wet etching to remove the not implanted hard mask layer; and performing an anisotropic dry etching to substantially remove the inner wall layer on the bottom of the deep trench so as to partially expose the trench capacitor and to substantially retain the collars of the deep trench capacitors intact.

Abstract: A method for preventing and/or ameliorating inflammation. The method comprises irradiating a biological subject with an electromagnetic wave from an emitter, wherein the electromagnetic wave has a wavelength of about 1.5 to 100 ?m ?m, and the biological subject can be a peripheral vascular disease patient. Additionally, the method of the invention can improve the access blood flow and unassisted patency of arteriovenous fistula in hemodialysis patients.

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

Abstract: Disclosed is a method for forming conducting wire and contact opening in a semiconductor device. The method comprises steps of providing a substrate; forming a first dielectric layer on the substrate; digging a via in the first dielectric layer and filling metal therein; forming a conductor layer on the first dielectric including the via; forming a metal layer on the conductor layer; removing unnecessary portions of the conductor/metal layers to define recesses, with the left portions to form conducting wires; applying a second dielectric layer to fill the recesses and performing planarization thereto to expose the conducting wires; forming a third dielectric layer; forming photoresist of predetermined pattern on the third dielectric layer; removing predetermined portion of the third dielectric layer to form a contact opening; and removing the photoresist.

Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract: A method of forming bit line contact. A substrate has device and peripheral contact areas, with the device area having transistors including a gate electrode, a doped region, and a pair of barrier spacers formed on opposing sidewalls of two adjacent gate electrodes. A dielectric layer is formed overlying the substrate, and a contact formed through the dielectric layer, exposing the doped region. Finally, a conductive layer is formed as a bit line contact plug to fill the bit line contact.

Abstract: A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.

Abstract: A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.