Abstract: Compared with the typical Si and GaAs material, a wide bandgap material (III-N compound) has the better electronic properties, particularly the operation stability and the temperature sensitivity, and is extremely suitable for the high power electronic application. The invention proposes a high power vertical GaN device for providing the reverse breakdown voltage higher than or equal to 600 V, the lower on-resistance is lower than or equal to 5 m?-cm2 and the forward current as high as 3 A/mm2.

Abstract: The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.

Abstract: The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

Abstract: A Schottky barrier diode (SBD) is disclosed, which includes: a gallium nitride (GaN) layer, formed on a substrate; an aluminum gallium nitride (AlGaN), formed on the GaN layer; an insulation layer, formed on the AlGaN layer; an anode conducive layer, formed on the insulation layer, wherein Schottky contact is formed between a part of the anode conductive layer and the AlGaN layer or between a part of the anode conductive layer and the GaN layer, and another part of the anode conductive layer is separated from the AlGaN layer by the insulation layer; and a cathode conductive layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the cathode conductive layer and the GaN layer or between the cathode conductive layer and the AlGaN layer, and wherein the anode conductive layer is not directly connected to the cathode conductive layer.

Abstract: The present invention discloses a Schottky barrier diode (SBD) and a manufacturing method thereof. The SBD is formed on a substrate. The SBD includes: a gallium nitride (GaN) layer; an aluminum gallium nitride (AlGaN), formed on the GaN layer; a high work function conductive layer, formed on the AlGaN layer, wherein a first Schottky contact is formed between the high work function conductive layer and the AlGaN layer; a low work function conductive layer, formed on the AlGaN layer, wherein a second Schottky contact is formed between the low work function conductive layer and the AlGaN layer; and an ohmic contact metal layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the ohmic contact metal layer and the AlGaN layer, and wherein the ohmic contact conductive layer is separated from the high and low work function conductive layers by a dielectric layer.

Abstract: In an image reading apparatus capable of separating pages of images, an automatic sheet feeder transports first and second documents along a document passageway and past an opening. A separation reference sheet is disposed in the opening and includes a specific portion. A scanning module scans the first and second documents, transported past the opening, to generate a continuous image. An image processing unit coupled to the scanning module receives the continuous image and processes the continuous image into a first document image corresponding to the first document and a second document image corresponding to the second document according to a specific image including the specific portion.

Abstract: A method of fabricating a silicon carbide (SiC) layer is disclosed, which comprises steps: (S1) heating a silicon-based substrate at a temperature of X ° C.; (S2) carburizating the silicon-based substrate with a first hydrocarbon-containing gas at a temperature of Y ° C. to form a carbide layer on the silicon-based substrate; (S3) annealing the silicon-based substrate with the carbide layer thereon at a temperature of Z ° C.; and (S4) forming a silicon carbide layer on the carbide layer with a second hydrocarbon-containing gas and a silicon-containing gas at a temperature of W ° C.; wherein, X is 800 to 1200; Y is 1100 to 1400; Z is 1200 to 1500; W is 1300 to 1550; and X<Y?Z?W. In the method of the present invention, since no cooling steps between respective steps are required, the full process time can be reduced and the cost is lowered because no energy consumption occurs for the cooling and the re-heating steps.

Abstract: A method of fabricating a silicon carbide (SiC) layer is disclosed, which comprises steps: (S1) heating a silicon-based substrate at a temperature of X ° C.; (S2) carburizating the silicon-based substrate with a first hydrocarbon-containing gas at a temperature of Y ° C. to form a carbide layer on the silicon-based substrate; (S3) annealing the silicon-based substrate with the carbide layer thereon at a temperature of Z ° C.; and (S4) forming a silicon carbide layer on the carbide layer with a second hydrocarbon-containing gas and a silicon-containing gas at a temperature of W ° C.; wherein, X is 800 to 1200; Y is 1100 to 1400; Z is 1200 to 1500; W is 1300 to 1550; and X<Y?Z?W. In the method of the present invention, since no cooling steps between respective steps are required, the full process time can be reduced and the cost is lowered because no energy consumption occurs for the cooling and the re-heating steps.

Abstract: In an image reading apparatus capable of separating pages of images, an automatic sheet feeder transports first and second documents along a document passageway and past an opening. A separation reference sheet is disposed in the opening and includes a specific portion. A scanning module scans the first and second documents, transported past the opening, to generate a continuous image. An image processing unit coupled to the scanning module receives the continuous image and processes the continuous image into a first document image corresponding to the first document and a second document image corresponding to the second document according to a specific image including the specific portion.

Abstract: A method of calibrating image luminance values is provided. At first, a calibration chart is scanned, and a dark actual luminance value and a white actual luminance value are obtained accordingly. Next, a document is scanned, and a scan luminance value is obtained accordingly. Then, a white ideal luminance value, a dark ideal luminance value, an ideal luminance value and a predetermined calibrated luminance value are provided. Next, a calibrated luminance value is determined according to the dark actual luminance value, the white actual luminance value, the white ideal luminance value, the dark ideal luminance value, the ideal luminance value, the predetermined calibrated luminance value and the scan luminance value.

Abstract: An improved LED chip packaging structure includes a substrate, an insulating layer, a light emitting chip and sealing adhesive. At least two conductive traces are disposed on at least one side surface of the substrate. The insulating layer attaches on one side surface of the substrate and includes an insulating film. The light emitting chip is received in the through hole of the insulating layer and attaches on one side surface of the substrate. An adhesive is securing the light emitting chip on the substrate, and the light emitting chip connects with at least one conducting wire. The sealing adhesive is filled into the through hole of the insulating layer. By the direct combination of the light emitting chip and the substrate, the present invention has the advantageous of low cost, the heat dispersal effect is improved, the packaging efficiency is increased, and the market competition is enhanced.

Abstract: A method of calibrating image luminance values is provided. Firstly, scan N calibration charts to obtain N corresponding actual luminance values, where N is a positive integer larger than 2. Next, scan a document to obtain a scan luminance value. Then, provide N ideal luminance values corresponding to the N calibration charts. Lastly, determine a calibrated luminance value according to the N actual luminance values, the N ideal luminance values and the scan luminance value.

Abstract: An improved LED chip packaging structure includes a substrate, an insulating layer, a light emitting chip and sealing adhesive. At least two conductive traces are disposed on at least one side surface of the substrate. The insulating layer attaches on one side surface of the substrate and includes an insulating film. The light emitting chip is received in the through hole of the insulating layer and attaches on one side surface of the substrate. An adhesive is securing the light emitting chip on the substrate, and the light emitting chip connects with at least one conducting wire. The sealing adhesive is filled into the through hole of the insulating layer. By the direct combination of the light emitting chip and the substrate, the present invention has the advantageous of low cost, the heat dispersal effect is improved, the packaging efficiency is increased, and the market competition is enhanced.

Abstract: A method of calibrating image luminance values is provided. At first, a calibration chart is scanned, and a dark actual luminance value and a white actual luminance value are obtained accordingly. Next, a document is scanned, and a scan luminance value is obtained accordingly. Then, a white ideal luminance value, a dark ideal luminance value, an ideal luminance value and a predetermined calibrated luminance value are provided. Next, a calibrated luminance value is determined according to the dark actual luminance value, the white actual luminance value, the white ideal luminance value, the dark ideal luminance value, the ideal luminance value, the predetermined calibrated luminance value and the scan luminance value.