Abstract: A start up circuit of power converters is presented. It includes a first transistor, a resistive device, a second transistor, a third transistor and a diode. The first transistor is coupled to a voltage source. The third transistor is connected in serial with the first transistor to output a supply voltage to a control circuit of the power converter in response to the voltage source. The diode is connected from a transformer winding of the power converter to supply a further supply voltage to the control circuit of the power converter. The second transistor is coupled to control the first transistor and the third transistor in response to a control signal. The resistive device provides a bias voltage to turn on the first transistor and the third transistor when the second transistor is turned off. Once the second transistor is turned on, the third transistor is turned off and the first transistor is negative biased.

Abstract: A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate and a deep well. The deep well is formed in the substrate and has a first concave structure. The ion-doped junction includes a semiconductor region connected to the first concave structure of the deep well and having substantially the same ion-doping concentration as the substrate.

Abstract: A power transistor chip with a built-in start-up transistor and an application circuit thereof provides a junction field effect transistor in association with a metal oxide semiconductor field effect transistor to act as a start-up circuit of an AC/DC voltage converter. The start-up circuit can be turned off after the PWM circuit of the AC/DC voltage converter operates normally to conserve the consumption of the power. Besides, the junction field effect transistor and the metal oxide semiconductor field effect transistor are built in the power transistor chip. Because the junction field effect transistor and the metal oxide semiconductor field effect are fabricated with the same manufacturing process as the power transistor, it is capable of simplifying the entire process and lowering the production cost due to no additional mask and manufacturing process.

Abstract: A power transistor chip and an application circuit thereof has a junction field effect transistor to act as a start-up circuit of an AC/DC voltage converter. The start-up circuit can be turned off after the PWM circuit of the AC/DC voltage converter operates normally to conserve the consumption of the power. Besides, the junction field effect transistor is built in the power transistor chip. Because the junction field effect transistor is fabricated with the same manufacturing process as the power transistor, it is capable of simplifying the entire process and lowering the production cost due to no additional mask and manufacturing process.

Abstract: A method for fabricating a junction field effect transistor includes the steps of the type I semiconductor at the base thereof being doped with the type II semiconductor to form a type II well with a hole; then, a drive-in process of the type II semiconductor is performed to allow the implant dosage of the type II well getting less gradually from the surroundings of the hole toward the center of the hole; and finally, the gate, the source and the drain of the junction field effect transistor being formed successively on the type II well. The implant dosage at the hole, which is acted as a channel, is determined in accordance with the preset size of the hole during the type II well being formed such that it is capable being compatible with the output voltages of different junction field effect transistors to achieve the purpose of the adjustment of the pinch-off voltage of the junction field effect transistor without the need of the mask and the manufacturing process.

Abstract: The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.

Abstract: The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.

Abstract: An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit function and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.

Abstract: A switching circuit for power converters is presented. It includes a voltage-clipping device, a resistive device, a first transistor and a second transistor. The voltage-clipping device is coupled to an input voltage. The first transistor is connected in series with the voltage-clipping device for switching the input voltage. The second transistor is coupled to control the first transistor and the voltage-clipping device in response to a control signal. The resistive device provides a bias voltage to turn on the voltage-clipping device and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the voltage-clipping device is negatively biased. The voltage-clipping device is developed to clamp a maximum voltage for the first transistor.

Abstract: A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate, a first deep well and a second deep well, a first heavy ion-doped region and a second heavy ion-doped region. The first deep well and second deep well are formed in the substrate, which are separated but partially linked with each other, and the first deep well and the second deep well have the same ion-doped type. The first heavy ion-doped region is formed in the first deep well for connecting to a first high voltage, and the first heavy ion-doped region has the same ion-doped type as the first deep well. The second heavy ion-doped region is formed in the second deep well for connecting to a second high voltage, and the second heavy ion-doped region has the same ion-doped type as the first deep well.

Abstract: A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.

Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.

Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.

Abstract: A semiconductor structure for protecting an internal integrated circuit comprises a substrate; a plurality of first doping regions formed in the substrate and disposed substantially within an N-well; a plurality of second doping regions, formed in the substrate and disposed within an P-well; a N+ section, formed in the substrate and enclosing the N-well and the P-well; a pad, formed above the substrate and electrically connected to at least one of the first doping regions; and a first ground and a second ground respectively disposed to positions corresponding to outside and inside of the N+ section. Also, the second doping regions are isolated from the first doping regions. The first and second doping regions located within the N+ section are isolated from the substrate by the N+ section. Furthermore, the second ground is electrically connected to at least one of the second doping regions.

Abstract: A semiconductor structure with high breakdown voltage and high resistance and method for manufacturing the same. The semiconductor structure at least comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; two first wells having the first conductive type and formed within the deep well; a second well having the first conductive type and formed between two first wells within the deep well, and a implant dosage of the second well lighter than a implant dosage of the first well; and two first doping regions having the first conductive type and respectively formed within the first wells.

Abstract: A start up circuit for power converters is presented. It includes a JFET transistor, a resistive device, a first transistor, a second transistor and a diode. The JFET transistor is coupled to a voltage source. The first transistor is connected in serial with the JFET transistor to output a supply voltage to a control circuit of the power converter. The diode is connected from a transformer winding of the power converter to supply a further supply voltage to the control circuit of the power converter. The second transistor is coupled to control the first transistor and the JFET transistor in response to a control signal. The resistive device provides a bias voltage to turn on the JFET transistor and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the JFET transistor is negative biased.

Abstract: The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential.

Abstract: An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.

Abstract: An ESD protection circuit is provided for protecting an integrated circuit from ESD damage and for protecting lightening surge. The ESD protection circuit includes a first snapback device and a second snapback device. The first snapback device is connected to a first terminal having a negative voltage of the integrated circuit during the operation of the integrated circuit. The first snapback device includes an anode coupled to the first terminal of the integrated circuit. The cathode of the first snapback device is coupled to a VCC terminal of the integrated circuit. The second snapback device has a cathode coupled to the VCC terminal. The anode of the second snapback device is connected to the ground of the integrated circuit. The snapback devices operate as silicon-controlled rectifiers (SCR) to protect the integrated circuit.

Abstract: A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage.