Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract: A semiconductor resistor and a semiconductor process of making the same are provided. The semiconductor resistor comprises a substrate, a deep well, at least two contact regions, and a doped region. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The contact regions are heavily doped with the second type of ions, and formed in the deep well. The doped region is doped with the first type of ions, and is separated from the deep well by a distance. Wherein the first type of ions and the second type of ions are complementary, and the distance between the deep well and the doped region adjusts the breakdown voltage. In addition, the semiconductor process comprises the steps of forming a deep well containing a first type of ions; forming a doped region containing a second type of ions; forming an oxide layer; and forming at least two contact regions containing the first type of ions in the deep well.

Abstract: Voltage-controlled semiconductor structures, voltage-controlled resistors, and manufacturing processes are provided. The semiconductor structure comprises a substrate, a first doped well, and a second doped well. The substrate is doped with a first type of ions. The first doped well is with a second type of ions and is formed in the substrate. The second doped well is with the second type of ions and is formed in the substrate. The first type of ions and the second type of ions are complementary. A resistor is formed between the first doped well and the second doped well. A resistivity of the resistor is controlled by a differential voltage. A resistivity of the resistor relates to a first depth of the first doped well, a second depth of the second doped well, and a distance between the first doped well and the second doped well. The resistivity of the resistor is higher than that of a well resistor formed in a single doped well with the second type of ions.

Abstract: The high voltage integrated circuit is disclosed. The high voltage integrated circuit comprises a low voltage control circuit, a floating circuit, a P substrate, a deep N well disposed in the substrate and a plurality of P wells disposed in the P substrate. The P wells and deep N well serve as the isolation structures. The low voltage control circuit is located outside the deep N well and the floating circuit is located inside the deep N well. The deep N well forms a high voltage junction barrier for isolating the control circuit from the floating circuit.

Abstract: A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate, a first deep well and a second deep well, a first heavy ion-doped region and a second heavy ion-doped region. The first deep well and second deep well are formed in the substrate, which are separated but partially linked with each other, and the first deep well and the second deep well have the same ion-doped type. The first heavy ion-doped region is formed in the first deep well for connecting to a first high voltage, and the first heavy ion-doped region has the same ion-doped type as the first deep well. The second heavy ion-doped region is formed in the second deep well for connecting to a second high voltage, and the second heavy ion-doped region has the same ion-doped type as the first deep well.

Abstract: A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate and a deep well. The deep well is formed in the substrate and has a first concave structure. The ion-doped junction includes a semiconductor region connected to the first concave structure of the deep well and having substantially the same ion-doping concentration as the substrate.

Abstract: The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.

Abstract: A semiconductor structure of a high side driver and method for manufacturing the same is disclosed. The semiconductor of a high side driver includes an ion-doped junction and an isolation layer formed on the ion-doped junction. The ion-doped junction has a number of ion-doped deep wells, and the ion-doped deep wells are separated but partially linked with each other.

Abstract: The present invention proposes a voltage-clipping device utilizing a pinch-off mechanism formed by two depletion boundaries. A clipping voltage of the voltage-clipping device can be adjusted in response to a gate voltage; a gap of a quasi-linked well; and a doping concentration and a depth of the quasi-linked well and a well with complementary doping polarity to the quasi-linked well. The voltage-clipping device can be integrated within a semiconductor device as a voltage stepping down device in a tiny size, compared to traditional transformers.

Abstract: The present invention provides a self-driven LDMOS, which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal will be clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS will be turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention doesn't lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential doesn't vary in response to an increment of the drain-voltage potential.

Abstract: A start up circuit of power converters is presented. It includes a first transistor, a resistive device, a second transistor, a third transistor and a diode. The first transistor is coupled to a voltage source. The third transistor is connected in serial with the first transistor to output a supply voltage to a control circuit of the power converter in response to the voltage source. The diode is connected from a transformer winding of the power converter to supply a further supply voltage to the control circuit of the power converter. The second transistor is coupled to control the first transistor and the third transistor in response to a control signal. The resistive device provides a bias voltage to turn on the first transistor and the third transistor when the second transistor is turned off. Once the second transistor is turned on, the third transistor is turned off and the first transistor is negative biased.

Abstract: A switching circuit for power converters is presented. It includes a voltage-clipping device, a resistive device, a first transistor and a second transistor. The voltage-clipping device is coupled to an input voltage. The first transistor is connected in series with the voltage-clipping device for switching the input voltage. The second transistor is coupled to control the first transistor and the voltage-clipping device in response to a control signal. The resistive device provides a bias voltage to turn on the voltage-clipping device and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the voltage-clipping device is negatively biased. The voltage-clipping device is developed to clamp a maximum voltage for the first transistor.

Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.

Abstract: A start up circuit for power converters is presented. It includes a JFET transistor, a resistive device, a first transistor, a second transistor and a diode. The JFET transistor is coupled to a voltage source. The first transistor is connected in serial with the JFET transistor to output a supply voltage to a control circuit of the power converter. The diode is connected from a transformer winding of the power converter to supply a further supply voltage to the control circuit of the power converter. The second transistor is coupled to control the first transistor and the JFET transistor in response to a control signal. The resistive device provides a bias voltage to turn on the JFET transistor and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the JFET transistor is negative biased.

Abstract: A switch circuit to control a high voltage source is presented. It includes a JFET transistor, a resistive device, a first transistor and a second transistor. The JFET transistor is coupled to the high voltage source. The first transistor is connected in serial with the JFET transistor to output a voltage in response to the high voltage source. The second transistor is coupled to control the first transistor and the JFET transistor in response to a control signal. The resistive device is coupled to the JFET transistor and the first transistor to provide a bias voltage to turn on the JFET transistor and the first transistor when the second transistor is turned off. Once the second transistor is turned on, the first transistor is turned off and the JFET transistor is negative biased.

Abstract: A keyboard and a method of applying in-mold decoration and ejaculation technology to manufacture the keyboard with more key height and less key spacing relates to a method of making a plastic film which includes a plurality of protruding portions, and cutting a plurality of protruding granules, and then applying the bottom base of the plurality of granules to integrate an elastic material layer to manufacture a keyboard; The gap between a plurality of keyboard's protruding portions is less than the protruding portions of the plastic film.

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Abstract: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region to respective well of rim core regions of the vertical transistor, the present invention realizes a stable breakdown voltage with short length of the field region. Therefore, the device area and the manufacturing cost can be reduced.

Abstract: A high resistance CMOS resistor with a relatively small die size is provided. The CMOS resistor includes a p-field region disposed in a n-well of a substrate and a pair of p-type contact regions respectively disposed beside a field oxide layer in the n-well. The pair of p-type contact regions are respectively connected to two sides of the p-field region as a first ohmic contact and a second ohmic contact for the CMOS resistor. The CMOS resistor according to the present invention has a resistance of, for example, 10 k?-20 k? per square.

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.